hypervisor: cpu: Introduce RISC-V specific error

Add error variants specific to RISC-V architecture.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
This commit is contained in:
Ruoqing He 2024-10-09 20:45:02 +08:00 committed by Rob Bradford
parent c5774685f4
commit c13019d5b5

View File

@ -216,6 +216,16 @@ pub enum HypervisorCpuError {
#[error("Failed to set aarch64 core register: {0}")] #[error("Failed to set aarch64 core register: {0}")]
SetAarchCoreRegister(#[source] anyhow::Error), SetAarchCoreRegister(#[source] anyhow::Error),
/// ///
/// Getting RISC-V 64-bit core register error
///
#[error("Failed to get riscv64 core register: {0}")]
GetRiscvCoreRegister(#[source] anyhow::Error),
///
/// Setting RISC-V 64-bit core register error
///
#[error("Failed to set riscv64 core register: {0}")]
SetRiscvCoreRegister(#[source] anyhow::Error),
///
/// Getting registers list error /// Getting registers list error
/// ///
#[error("Failed to retrieve list of registers: {0}")] #[error("Failed to retrieve list of registers: {0}")]
@ -231,6 +241,16 @@ pub enum HypervisorCpuError {
#[error("Failed to set system register: {0}")] #[error("Failed to set system register: {0}")]
SetSysRegister(#[source] anyhow::Error), SetSysRegister(#[source] anyhow::Error),
/// ///
/// Getting RISC-V 64-bit non-core register error
///
#[error("Failed to get non-core register: {0}")]
GetNonCoreRegister(#[source] anyhow::Error),
///
/// Setting RISC-V 64-bit non-core register error
///
#[error("Failed to set non-core register: {0}")]
SetNonCoreRegister(#[source] anyhow::Error),
///
/// GVA translation error /// GVA translation error
/// ///
#[error("Failed to translate GVA: {0}")] #[error("Failed to translate GVA: {0}")]