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hypervisor: cpu: Introduce RISC-V specific error
Add error variants specific to RISC-V architecture. Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
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@ -216,6 +216,16 @@ pub enum HypervisorCpuError {
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#[error("Failed to set aarch64 core register: {0}")]
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#[error("Failed to set aarch64 core register: {0}")]
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SetAarchCoreRegister(#[source] anyhow::Error),
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SetAarchCoreRegister(#[source] anyhow::Error),
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///
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///
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/// Getting RISC-V 64-bit core register error
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///
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#[error("Failed to get riscv64 core register: {0}")]
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GetRiscvCoreRegister(#[source] anyhow::Error),
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///
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/// Setting RISC-V 64-bit core register error
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///
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#[error("Failed to set riscv64 core register: {0}")]
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SetRiscvCoreRegister(#[source] anyhow::Error),
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///
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/// Getting registers list error
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/// Getting registers list error
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///
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///
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#[error("Failed to retrieve list of registers: {0}")]
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#[error("Failed to retrieve list of registers: {0}")]
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@ -231,6 +241,16 @@ pub enum HypervisorCpuError {
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#[error("Failed to set system register: {0}")]
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#[error("Failed to set system register: {0}")]
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SetSysRegister(#[source] anyhow::Error),
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SetSysRegister(#[source] anyhow::Error),
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///
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///
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/// Getting RISC-V 64-bit non-core register error
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///
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#[error("Failed to get non-core register: {0}")]
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GetNonCoreRegister(#[source] anyhow::Error),
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///
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/// Setting RISC-V 64-bit non-core register error
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///
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#[error("Failed to set non-core register: {0}")]
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SetNonCoreRegister(#[source] anyhow::Error),
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///
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/// GVA translation error
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/// GVA translation error
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///
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///
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#[error("Failed to translate GVA: {0}")]
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#[error("Failed to translate GVA: {0}")]
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