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pci: Refine detection of BAR reprogramming
The current code was always considering 0xffffffff being written to the register as a sign it was expecting to get the size, hence the BAR reprogramming detection was stating this case was not a reprogramming case. Problem is, if the value 0xffffffff is directed at a 64bits BAR, this might be the high or low part of a 64bits address which is meant to be the new address of the BAR, which means we would miss the detection of the BAR being reprogrammed here. This commit improves the code using finer granularity checks in order to detect this corner case correctly. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
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07bad79fd7
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c2ae380503
@ -674,10 +674,6 @@ impl PciConfiguration {
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let value = LittleEndian::read_u32(data);
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if value == 0xffff_ffff {
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return None;
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}
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let mask = self.writable_bits[reg_idx];
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if reg_idx >= BAR0_REG && reg_idx < BAR0_REG + NUM_BAR_REGS {
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let bar_idx = reg_idx - 4;
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@ -689,6 +685,12 @@ impl PciConfiguration {
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match bar_type {
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PciBarRegionType::Memory64BitRegion => {}
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_ => {
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// Ignore the case where the BAR size is being
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// asked for.
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if value == 0xffff_ffff {
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return None;
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}
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debug!(
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"DETECT BAR REPROG: current 0x{:x}, new 0x{:x}",
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self.registers[reg_idx], value
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@ -712,6 +714,17 @@ impl PciConfiguration {
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&& (self.registers[reg_idx - 1] & self.writable_bits[reg_idx - 1])
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!= (self.bar_addr[bar_idx - 1] & self.writable_bits[reg_idx - 1])
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{
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// Ignore the case where the BAR size is being asked for.
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// Because we are in the 64bits case here, we have to check
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// if the lower 32bits of the current BAR have already been
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// asked for the BAR size too.
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if value == 0xffff_ffff
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&& self.registers[reg_idx - 1] & self.writable_bits[reg_idx - 1]
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== self.bar_size[bar_idx - 1] & self.writable_bits[reg_idx - 1]
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{
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return None;
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}
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debug!(
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"DETECT BAR REPROG: current 0x{:x}, new 0x{:x}",
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self.registers[reg_idx], value
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