mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
synced 2024-12-22 05:35:20 +00:00
vm-virtio: Add PCI transport support
Copied from crosvm 107edb3e with one main modification: VirtioPciDevice implements BusDevice. We need this modification because it is the only way for us to be able to add a VirtioPciDevice to the MMIO bus. Bus insertion takes a BusDevice. The fact that VirtioPciDevice implements PciDevice which itself implements BusDevice does not mean that Rust will automatically downcast a VirtioPciDevice into a BusDevice. crosvm works around that issue by having the PCI, virtio and BusDevice implementations in the same crate. Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Samuel Ortiz
parent
8246434710
commit
c2c51dc9d1
@ -20,20 +20,17 @@ use std::io;
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mod device;
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mod queue;
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pub mod transport;
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pub use self::device::*;
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pub use self::queue::*;
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#[allow(dead_code)]
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const DEVICE_INIT: u32 = 0x00;
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#[allow(dead_code)]
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const DEVICE_ACKNOWLEDGE: u32 = 0x01;
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#[allow(dead_code)]
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const DEVICE_DRIVER: u32 = 0x02;
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#[allow(dead_code)]
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const DEVICE_DRIVER_OK: u32 = 0x04;
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#[allow(dead_code)]
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const DEVICE_FEATURES_OK: u32 = 0x08;
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#[allow(dead_code)]
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const DEVICE_FAILED: u32 = 0x80;
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#[allow(dead_code)]
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7
vm-virtio/src/transport/mod.rs
Normal file
7
vm-virtio/src/transport/mod.rs
Normal file
@ -0,0 +1,7 @@
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// Copyright (c) 2019 Intel
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mod pci_common_config;
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mod pci_device;
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pub use pci_common_config::VirtioPciCommonConfig;
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pub use pci_device::VirtioPciDevice;
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335
vm-virtio/src/transport/pci_common_config.rs
Normal file
335
vm-virtio/src/transport/pci_common_config.rs
Normal file
@ -0,0 +1,335 @@
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// Copyright 2018 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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extern crate byteorder;
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use byteorder::{ByteOrder, LittleEndian};
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use vm_memory::GuestAddress;
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use crate::{Queue, VirtioDevice};
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/// Contains the data for reading and writing the common configuration structure of a virtio PCI
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/// device.
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///
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/// * Registers:
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/// ** About the whole device.
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/// le32 device_feature_select; // 0x00 // read-write
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/// le32 device_feature; // 0x04 // read-only for driver
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/// le32 driver_feature_select; // 0x08 // read-write
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/// le32 driver_feature; // 0x0C // read-write
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/// le16 msix_config; // 0x10 // read-write
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/// le16 num_queues; // 0x12 // read-only for driver
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/// u8 device_status; // 0x14 // read-write (driver_status)
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/// u8 config_generation; // 0x15 // read-only for driver
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/// ** About a specific virtqueue.
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/// le16 queue_select; // 0x16 // read-write
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/// le16 queue_size; // 0x18 // read-write, power of 2, or 0.
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/// le16 queue_msix_vector; // 0x1A // read-write
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/// le16 queue_enable; // 0x1C // read-write (Ready)
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/// le16 queue_notify_off; // 0x1E // read-only for driver
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/// le64 queue_desc; // 0x20 // read-write
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/// le64 queue_avail; // 0x28 // read-write
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/// le64 queue_used; // 0x30 // read-write
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pub struct VirtioPciCommonConfig {
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pub driver_status: u8,
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pub config_generation: u8,
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pub device_feature_select: u32,
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pub driver_feature_select: u32,
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pub queue_select: u16,
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}
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impl VirtioPciCommonConfig {
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pub fn read(
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&mut self,
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offset: u64,
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data: &mut [u8],
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queues: &mut Vec<Queue>,
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device: &mut dyn VirtioDevice,
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) {
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assert!(data.len() <= 8);
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match data.len() {
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1 => {
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let v = self.read_common_config_byte(offset);
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data[0] = v;
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}
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2 => {
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let v = self.read_common_config_word(offset, queues);
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LittleEndian::write_u16(data, v);
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}
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4 => {
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let v = self.read_common_config_dword(offset, device);
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LittleEndian::write_u32(data, v);
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}
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8 => {
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let v = self.read_common_config_qword(offset);
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LittleEndian::write_u64(data, v);
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}
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_ => error!("invalid data length for virtio read: len {}", data.len()),
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}
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}
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pub fn write(
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&mut self,
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offset: u64,
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data: &[u8],
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queues: &mut Vec<Queue>,
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device: &mut dyn VirtioDevice,
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) {
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assert!(data.len() <= 8);
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match data.len() {
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1 => self.write_common_config_byte(offset, data[0]),
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2 => self.write_common_config_word(offset, LittleEndian::read_u16(data), queues),
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4 => {
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self.write_common_config_dword(offset, LittleEndian::read_u32(data), queues, device)
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}
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8 => self.write_common_config_qword(offset, LittleEndian::read_u64(data), queues),
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_ => error!("invalid data length for virtio write: len {}", data.len()),
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}
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}
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fn read_common_config_byte(&self, offset: u64) -> u8 {
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debug!("read_common_config_byte: offset 0x{:x}", offset);
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// The driver is only allowed to do aligned, properly sized access.
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match offset {
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0x14 => self.driver_status,
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0x15 => self.config_generation,
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_ => {
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warn!("invalid virtio config byte read: 0x{:x}", offset);
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0
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}
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}
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}
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fn write_common_config_byte(&mut self, offset: u64, value: u8) {
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debug!("write_common_config_byte: offset 0x{:x}", offset);
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match offset {
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0x14 => self.driver_status = value,
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_ => {
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warn!("invalid virtio config byte write: 0x{:x}", offset);
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}
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}
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}
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fn read_common_config_word(&self, offset: u64, queues: &[Queue]) -> u16 {
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debug!("read_common_config_word: offset 0x{:x}", offset);
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match offset {
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0x10 => 0, // TODO msi-x (crbug/854765): self.msix_config,
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0x12 => queues.len() as u16, // num_queues
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0x16 => self.queue_select,
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0x18 => self.with_queue(queues, |q| q.size).unwrap_or(0),
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0x1c => {
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if self.with_queue(queues, |q| q.ready).unwrap_or(false) {
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1
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} else {
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0
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}
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}
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0x1e => self.queue_select, // notify_off
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_ => {
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warn!("invalid virtio register word read: 0x{:x}", offset);
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0
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}
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}
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}
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fn write_common_config_word(&mut self, offset: u64, value: u16, queues: &mut Vec<Queue>) {
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debug!("write_common_config_word: offset 0x{:x}", offset);
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match offset {
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0x10 => (), // TODO msi-x (crbug/854765): self.msix_config = value,
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0x16 => self.queue_select = value,
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0x18 => self.with_queue_mut(queues, |q| q.size = value),
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0x1a => (), // TODO msi-x (crbug/854765): self.with_queue_mut(queues, |q| q.msix_vector = v),
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0x1c => self.with_queue_mut(queues, |q| q.ready = value == 1),
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_ => {
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warn!("invalid virtio register word write: 0x{:x}", offset);
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}
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}
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}
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fn read_common_config_dword(&self, offset: u64, device: &dyn VirtioDevice) -> u32 {
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debug!("read_common_config_dword: offset 0x{:x}", offset);
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match offset {
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0x00 => self.device_feature_select,
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0x04 => {
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// Only 64 bits of features (2 pages) are defined for now, so limit
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// device_feature_select to avoid shifting by 64 or more bits.
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if self.device_feature_select < 2 {
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device.features(self.device_feature_select)
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} else {
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0
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}
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}
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0x08 => self.driver_feature_select,
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_ => {
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warn!("invalid virtio register dword read: 0x{:x}", offset);
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0
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}
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}
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}
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fn write_common_config_dword(
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&mut self,
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offset: u64,
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value: u32,
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queues: &mut Vec<Queue>,
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device: &mut dyn VirtioDevice,
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) {
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debug!("write_common_config_dword: offset 0x{:x}", offset);
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fn hi(v: &mut GuestAddress, x: u32) {
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*v = (*v & 0xffff_ffff) | ((u64::from(x)) << 32)
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}
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fn lo(v: &mut GuestAddress, x: u32) {
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*v = (*v & !0xffff_ffff) | (u64::from(x))
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}
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match offset {
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0x00 => self.device_feature_select = value,
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0x08 => self.driver_feature_select = value,
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0x0c => {
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if self.driver_feature_select < 2 {
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device.ack_features(self.driver_feature_select, value);
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} else {
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warn!(
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"invalid ack_features (page {}, value 0x{:x})",
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self.driver_feature_select, value
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);
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}
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}
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0x20 => self.with_queue_mut(queues, |q| lo(&mut q.desc_table, value)),
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0x24 => self.with_queue_mut(queues, |q| hi(&mut q.desc_table, value)),
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0x28 => self.with_queue_mut(queues, |q| lo(&mut q.avail_ring, value)),
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0x2c => self.with_queue_mut(queues, |q| hi(&mut q.avail_ring, value)),
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0x30 => self.with_queue_mut(queues, |q| lo(&mut q.used_ring, value)),
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0x34 => self.with_queue_mut(queues, |q| hi(&mut q.used_ring, value)),
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_ => {
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warn!("invalid virtio register dword write: 0x{:x}", offset);
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}
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}
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}
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fn read_common_config_qword(&self, _offset: u64) -> u64 {
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debug!("read_common_config_qword: offset 0x{:x}", _offset);
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0 // Assume the guest has no reason to read write-only registers.
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}
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fn write_common_config_qword(&mut self, offset: u64, value: u64, queues: &mut Vec<Queue>) {
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debug!("write_common_config_qword: offset 0x{:x}", offset);
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match offset {
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0x20 => self.with_queue_mut(queues, |q| q.desc_table = GuestAddress(value)),
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0x28 => self.with_queue_mut(queues, |q| q.avail_ring = GuestAddress(value)),
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0x30 => self.with_queue_mut(queues, |q| q.used_ring = GuestAddress(value)),
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_ => {
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warn!("invalid virtio register qword write: 0x{:x}", offset);
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}
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}
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}
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fn with_queue<U, F>(&self, queues: &[Queue], f: F) -> Option<U>
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where
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F: FnOnce(&Queue) -> U,
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{
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queues.get(self.queue_select as usize).map(f)
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}
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fn with_queue_mut<F: FnOnce(&mut Queue)>(&self, queues: &mut Vec<Queue>, f: F) {
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if let Some(queue) = queues.get_mut(self.queue_select as usize) {
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f(queue);
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}
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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use crate::ActivateResult;
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use std::sync::atomic::AtomicUsize;
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use std::sync::Arc;
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use vm_memory::GuestMemoryMmap;
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use vmm_sys_util::EventFd;
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struct DummyDevice(u32);
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const QUEUE_SIZE: u16 = 256;
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const QUEUE_SIZES: &'static [u16] = &[QUEUE_SIZE];
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const DUMMY_FEATURES: u64 = 0x5555_aaaa;
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impl VirtioDevice for DummyDevice {
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fn device_type(&self) -> u32 {
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return self.0;
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}
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fn queue_max_sizes(&self) -> &[u16] {
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QUEUE_SIZES
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}
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fn activate(
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&mut self,
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_mem: GuestMemoryMmap,
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_interrupt_evt: EventFd,
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_status: Arc<AtomicUsize>,
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_queues: Vec<Queue>,
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_queue_evts: Vec<EventFd>,
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) -> ActivateResult {
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Ok(())
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}
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fn features(&self, _page: u32) -> u32 {
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DUMMY_FEATURES as u32
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}
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fn ack_features(&mut self, _page: u32, _value: u32) {}
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fn read_config(&self, _offset: u64, _data: &mut [u8]) {}
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fn write_config(&mut self, _offset: u64, _data: &[u8]) {}
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}
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#[test]
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fn write_base_regs() {
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let mut regs = VirtioPciCommonConfig {
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driver_status: 0xaa,
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config_generation: 0x55,
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device_feature_select: 0x0,
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driver_feature_select: 0x0,
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queue_select: 0xff,
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};
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let dev = &mut DummyDevice(0) as &mut dyn VirtioDevice;
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let mut queues = Vec::new();
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// Can set all bits of driver_status.
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regs.write(0x14, &[0x55], &mut queues, dev);
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let mut read_back = vec![0x00];
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regs.read(0x14, &mut read_back, &mut queues, dev);
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assert_eq!(read_back[0], 0x55);
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// The config generation register is read only.
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regs.write(0x15, &[0xaa], &mut queues, dev);
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let mut read_back = vec![0x00];
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regs.read(0x15, &mut read_back, &mut queues, dev);
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assert_eq!(read_back[0], 0x55);
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// Device features is read-only and passed through from the device.
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regs.write(0x04, &[0, 0, 0, 0], &mut queues, dev);
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let mut read_back = vec![0, 0, 0, 0];
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regs.read(0x04, &mut read_back, &mut queues, dev);
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assert_eq!(LittleEndian::read_u32(&read_back), DUMMY_FEATURES as u32);
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// Feature select registers are read/write.
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regs.write(0x00, &[1, 2, 3, 4], &mut queues, dev);
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let mut read_back = vec![0, 0, 0, 0];
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regs.read(0x00, &mut read_back, &mut queues, dev);
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assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
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regs.write(0x08, &[1, 2, 3, 4], &mut queues, dev);
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let mut read_back = vec![0, 0, 0, 0];
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regs.read(0x08, &mut read_back, &mut queues, dev);
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assert_eq!(LittleEndian::read_u32(&read_back), 0x0403_0201);
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// 'queue_select' can be read and written.
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regs.write(0x16, &[0xaa, 0x55], &mut queues, dev);
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let mut read_back = vec![0x00, 0x00];
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regs.read(0x16, &mut read_back, &mut queues, dev);
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assert_eq!(read_back[0], 0xaa);
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assert_eq!(read_back[1], 0x55);
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}
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}
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461
vm-virtio/src/transport/pci_device.rs
Executable file
461
vm-virtio/src/transport/pci_device.rs
Executable file
@ -0,0 +1,461 @@
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// Copyright 2018 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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extern crate devices;
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extern crate pci;
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extern crate vm_allocator;
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extern crate vm_memory;
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extern crate vmm_sys_util;
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use byteorder::{ByteOrder, LittleEndian};
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use libc::EFD_NONBLOCK;
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use std::sync::atomic::{AtomicUsize, Ordering};
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use std::sync::Arc;
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use devices::BusDevice;
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use pci::{
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PciBarConfiguration, PciCapability, PciCapabilityID, PciClassCode, PciConfiguration, PciDevice,
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PciDeviceError, PciHeaderType, PciInterruptPin, PciSubclass,
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};
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use vm_allocator::SystemAllocator;
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use vm_memory::{Address, ByteValued, GuestAddress, GuestMemoryMmap, GuestUsize, Le32};
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use vmm_sys_util::{EventFd, Result};
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use super::VirtioPciCommonConfig;
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use crate::{
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Queue, VirtioDevice, DEVICE_ACKNOWLEDGE, DEVICE_DRIVER, DEVICE_DRIVER_OK, DEVICE_FAILED,
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DEVICE_FEATURES_OK,
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};
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#[allow(clippy::enum_variant_names)]
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enum PciCapabilityType {
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CommonConfig = 1,
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NotifyConfig = 2,
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IsrConfig = 3,
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DeviceConfig = 4,
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PciConfig = 5,
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}
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#[allow(dead_code)]
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#[repr(packed)]
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#[derive(Clone, Copy, Default)]
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struct VirtioPciCap {
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cap_len: u8, // Generic PCI field: capability length
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cfg_type: u8, // Identifies the structure.
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pci_bar: u8, // Where to find it.
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padding: [u8; 3], // Pad to full dword.
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offset: Le32, // Offset within bar.
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length: Le32, // Length of the structure, in bytes.
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}
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// It is safe to implement ByteValued. All members are simple numbers and any value is valid.
|
||||
unsafe impl ByteValued for VirtioPciCap {}
|
||||
|
||||
impl PciCapability for VirtioPciCap {
|
||||
fn bytes(&self) -> &[u8] {
|
||||
self.as_slice()
|
||||
}
|
||||
|
||||
fn id(&self) -> PciCapabilityID {
|
||||
PciCapabilityID::VendorSpecific
|
||||
}
|
||||
}
|
||||
|
||||
const VIRTIO_PCI_CAPABILITY_BYTES: u8 = 16;
|
||||
|
||||
impl VirtioPciCap {
|
||||
pub fn new(cfg_type: PciCapabilityType, pci_bar: u8, offset: u32, length: u32) -> Self {
|
||||
VirtioPciCap {
|
||||
cap_len: VIRTIO_PCI_CAPABILITY_BYTES,
|
||||
cfg_type: cfg_type as u8,
|
||||
pci_bar,
|
||||
padding: [0; 3],
|
||||
offset: Le32::from(offset),
|
||||
length: Le32::from(length),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
#[repr(packed)]
|
||||
#[derive(Clone, Copy, Default)]
|
||||
struct VirtioPciNotifyCap {
|
||||
cap: VirtioPciCap,
|
||||
notify_off_multiplier: Le32,
|
||||
}
|
||||
// It is safe to implement ByteValued. All members are simple numbers and any value is valid.
|
||||
unsafe impl ByteValued for VirtioPciNotifyCap {}
|
||||
|
||||
impl PciCapability for VirtioPciNotifyCap {
|
||||
fn bytes(&self) -> &[u8] {
|
||||
self.as_slice()
|
||||
}
|
||||
|
||||
fn id(&self) -> PciCapabilityID {
|
||||
PciCapabilityID::VendorSpecific
|
||||
}
|
||||
}
|
||||
|
||||
impl VirtioPciNotifyCap {
|
||||
pub fn new(
|
||||
cfg_type: PciCapabilityType,
|
||||
pci_bar: u8,
|
||||
offset: u32,
|
||||
length: u32,
|
||||
multiplier: Le32,
|
||||
) -> Self {
|
||||
VirtioPciNotifyCap {
|
||||
cap: VirtioPciCap {
|
||||
cap_len: std::mem::size_of::<VirtioPciNotifyCap>() as u8,
|
||||
cfg_type: cfg_type as u8,
|
||||
pci_bar,
|
||||
padding: [0; 3],
|
||||
offset: Le32::from(offset),
|
||||
length: Le32::from(length),
|
||||
},
|
||||
notify_off_multiplier: multiplier,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
#[derive(Copy, Clone)]
|
||||
pub enum PciVirtioSubclass {
|
||||
NonTransitionalBase = 0xff,
|
||||
}
|
||||
|
||||
impl PciSubclass for PciVirtioSubclass {
|
||||
fn get_register_value(&self) -> u8 {
|
||||
*self as u8
|
||||
}
|
||||
}
|
||||
|
||||
// Allocate one bar for the structs pointed to by the capability structures.
|
||||
const COMMON_CONFIG_BAR_OFFSET: u64 = 0x0000;
|
||||
const COMMON_CONFIG_SIZE: u64 = 56;
|
||||
const ISR_CONFIG_BAR_OFFSET: u64 = 0x1000;
|
||||
const ISR_CONFIG_SIZE: u64 = 1;
|
||||
const DEVICE_CONFIG_BAR_OFFSET: u64 = 0x2000;
|
||||
const DEVICE_CONFIG_SIZE: u64 = 0x1000;
|
||||
const NOTIFICATION_BAR_OFFSET: u64 = 0x3000;
|
||||
const NOTIFICATION_SIZE: u64 = 0x1000;
|
||||
const CAPABILITY_BAR_SIZE: u64 = 0x4000;
|
||||
|
||||
const NOTIFY_OFF_MULTIPLIER: u32 = 4; // A dword per notification address.
|
||||
|
||||
const VIRTIO_PCI_VENDOR_ID: u16 = 0x1af4;
|
||||
const VIRTIO_PCI_DEVICE_ID_BASE: u16 = 0x1040; // Add to device type to get device ID.
|
||||
|
||||
pub struct VirtioPciDevice {
|
||||
// PCI configuration registers.
|
||||
configuration: PciConfiguration,
|
||||
|
||||
// virtio PCI common configuration
|
||||
common_config: VirtioPciCommonConfig,
|
||||
|
||||
// Virtio device reference and status
|
||||
device: Box<VirtioDevice>,
|
||||
device_activated: bool,
|
||||
|
||||
// PCI interrupts.
|
||||
interrupt_status: Arc<AtomicUsize>,
|
||||
interrupt_evt: Option<EventFd>,
|
||||
|
||||
// virtio queues
|
||||
queues: Vec<Queue>,
|
||||
queue_evts: Vec<EventFd>,
|
||||
|
||||
// Guest memory
|
||||
memory: Option<GuestMemoryMmap>,
|
||||
|
||||
// Setting PCI BAR
|
||||
settings_bar: u8,
|
||||
}
|
||||
|
||||
impl VirtioPciDevice {
|
||||
/// Constructs a new PCI transport for the given virtio device.
|
||||
pub fn new(memory: GuestMemoryMmap, device: Box<VirtioDevice>) -> Result<Self> {
|
||||
let mut queue_evts = Vec::new();
|
||||
for _ in device.queue_max_sizes().iter() {
|
||||
queue_evts.push(EventFd::new(EFD_NONBLOCK)?)
|
||||
}
|
||||
let queues = device
|
||||
.queue_max_sizes()
|
||||
.iter()
|
||||
.map(|&s| Queue::new(s))
|
||||
.collect();
|
||||
|
||||
let pci_device_id = VIRTIO_PCI_DEVICE_ID_BASE + device.device_type() as u16;
|
||||
|
||||
let configuration = PciConfiguration::new(
|
||||
VIRTIO_PCI_VENDOR_ID,
|
||||
pci_device_id,
|
||||
PciClassCode::Other,
|
||||
&PciVirtioSubclass::NonTransitionalBase,
|
||||
None,
|
||||
PciHeaderType::Device,
|
||||
VIRTIO_PCI_VENDOR_ID,
|
||||
pci_device_id,
|
||||
);
|
||||
|
||||
Ok(VirtioPciDevice {
|
||||
configuration,
|
||||
common_config: VirtioPciCommonConfig {
|
||||
driver_status: 0,
|
||||
config_generation: 0,
|
||||
device_feature_select: 0,
|
||||
driver_feature_select: 0,
|
||||
queue_select: 0,
|
||||
},
|
||||
device,
|
||||
device_activated: false,
|
||||
interrupt_status: Arc::new(AtomicUsize::new(0)),
|
||||
interrupt_evt: None,
|
||||
queues,
|
||||
queue_evts,
|
||||
memory: Some(memory),
|
||||
settings_bar: 0,
|
||||
})
|
||||
}
|
||||
|
||||
fn is_driver_ready(&self) -> bool {
|
||||
let ready_bits =
|
||||
(DEVICE_ACKNOWLEDGE | DEVICE_DRIVER | DEVICE_DRIVER_OK | DEVICE_FEATURES_OK) as u8;
|
||||
self.common_config.driver_status == ready_bits
|
||||
&& self.common_config.driver_status & DEVICE_FAILED as u8 == 0
|
||||
}
|
||||
|
||||
fn are_queues_valid(&self) -> bool {
|
||||
if let Some(mem) = self.memory.as_ref() {
|
||||
self.queues.iter().all(|q| q.is_valid(mem))
|
||||
} else {
|
||||
false
|
||||
}
|
||||
}
|
||||
|
||||
fn add_pci_capabilities(
|
||||
&mut self,
|
||||
settings_bar: u8,
|
||||
) -> std::result::Result<(), PciDeviceError> {
|
||||
// Add pointers to the different configuration structures from the PCI capabilities.
|
||||
let common_cap = VirtioPciCap::new(
|
||||
PciCapabilityType::CommonConfig,
|
||||
settings_bar,
|
||||
COMMON_CONFIG_BAR_OFFSET as u32,
|
||||
COMMON_CONFIG_SIZE as u32,
|
||||
);
|
||||
self.configuration
|
||||
.add_capability(&common_cap)
|
||||
.map_err(PciDeviceError::CapabilitiesSetup)?;
|
||||
|
||||
let isr_cap = VirtioPciCap::new(
|
||||
PciCapabilityType::IsrConfig,
|
||||
settings_bar,
|
||||
ISR_CONFIG_BAR_OFFSET as u32,
|
||||
ISR_CONFIG_SIZE as u32,
|
||||
);
|
||||
self.configuration
|
||||
.add_capability(&isr_cap)
|
||||
.map_err(PciDeviceError::CapabilitiesSetup)?;
|
||||
|
||||
// TODO(dgreid) - set based on device's configuration size?
|
||||
let device_cap = VirtioPciCap::new(
|
||||
PciCapabilityType::DeviceConfig,
|
||||
settings_bar,
|
||||
DEVICE_CONFIG_BAR_OFFSET as u32,
|
||||
DEVICE_CONFIG_SIZE as u32,
|
||||
);
|
||||
self.configuration
|
||||
.add_capability(&device_cap)
|
||||
.map_err(PciDeviceError::CapabilitiesSetup)?;
|
||||
|
||||
let notify_cap = VirtioPciNotifyCap::new(
|
||||
PciCapabilityType::NotifyConfig,
|
||||
settings_bar,
|
||||
NOTIFICATION_BAR_OFFSET as u32,
|
||||
NOTIFICATION_SIZE as u32,
|
||||
Le32::from(NOTIFY_OFF_MULTIPLIER),
|
||||
);
|
||||
self.configuration
|
||||
.add_capability(¬ify_cap)
|
||||
.map_err(PciDeviceError::CapabilitiesSetup)?;
|
||||
|
||||
//TODO(dgreid) - How will the configuration_cap work?
|
||||
let configuration_cap = VirtioPciCap::new(PciCapabilityType::PciConfig, 0, 0, 0);
|
||||
self.configuration
|
||||
.add_capability(&configuration_cap)
|
||||
.map_err(PciDeviceError::CapabilitiesSetup)?;
|
||||
|
||||
self.settings_bar = settings_bar;
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
impl PciDevice for VirtioPciDevice {
|
||||
fn assign_irq(&mut self, irq_evt: EventFd, irq_num: u32, irq_pin: PciInterruptPin) {
|
||||
self.configuration.set_irq(irq_num as u8, irq_pin);
|
||||
self.interrupt_evt = Some(irq_evt);
|
||||
}
|
||||
|
||||
fn config_registers(&self) -> &PciConfiguration {
|
||||
&self.configuration
|
||||
}
|
||||
|
||||
fn config_registers_mut(&mut self) -> &mut PciConfiguration {
|
||||
&mut self.configuration
|
||||
}
|
||||
|
||||
fn allocate_bars(
|
||||
&mut self,
|
||||
allocator: &mut SystemAllocator,
|
||||
) -> std::result::Result<Vec<(GuestAddress, GuestUsize)>, PciDeviceError> {
|
||||
let mut ranges = Vec::new();
|
||||
|
||||
// Allocate the virtio-pci capability BAR.
|
||||
// See http://docs.oasis-open.org/virtio/virtio/v1.0/cs04/virtio-v1.0-cs04.html#x1-740004
|
||||
let virtio_pci_bar_addr = allocator
|
||||
.allocate_mmio_addresses(None, CAPABILITY_BAR_SIZE)
|
||||
.ok_or(PciDeviceError::IoAllocationFailed(CAPABILITY_BAR_SIZE))?;
|
||||
let config = PciBarConfiguration::default()
|
||||
.set_register_index(0)
|
||||
.set_address(virtio_pci_bar_addr.raw_value())
|
||||
.set_size(CAPABILITY_BAR_SIZE);
|
||||
let virtio_pci_bar =
|
||||
self.configuration.add_pci_bar(&config).map_err(|e| {
|
||||
PciDeviceError::IoRegistrationFailed(virtio_pci_bar_addr.raw_value(), e)
|
||||
})? as u8;
|
||||
|
||||
println!(
|
||||
"VIRTIO PCI BAR starts at 0x{:x}",
|
||||
virtio_pci_bar_addr.raw_value()
|
||||
);
|
||||
ranges.push((virtio_pci_bar_addr, CAPABILITY_BAR_SIZE));
|
||||
|
||||
// Once the BARs are allocated, the capabilities can be added to the PCI configuration.
|
||||
self.add_pci_capabilities(virtio_pci_bar)?;
|
||||
|
||||
// Allocate the device specific BARs.
|
||||
for config in self.device.get_device_bars() {
|
||||
let device_bar_addr = allocator
|
||||
.allocate_mmio_addresses(None, config.get_size())
|
||||
.ok_or_else(|| PciDeviceError::IoAllocationFailed(config.get_size()))?;
|
||||
config.set_address(device_bar_addr.raw_value());
|
||||
let _device_bar = self.configuration.add_pci_bar(&config).map_err(|e| {
|
||||
PciDeviceError::IoRegistrationFailed(device_bar_addr.raw_value(), e)
|
||||
})?;
|
||||
ranges.push((device_bar_addr, config.get_size()));
|
||||
}
|
||||
|
||||
Ok(ranges)
|
||||
}
|
||||
|
||||
fn read_bar(&mut self, addr: u64, data: &mut [u8]) {
|
||||
// The driver is only allowed to do aligned, properly sized access.
|
||||
let bar0 = u64::from(self.configuration.get_bar_addr(self.settings_bar as usize));
|
||||
let offset = addr - bar0;
|
||||
match offset {
|
||||
o if o < COMMON_CONFIG_BAR_OFFSET + COMMON_CONFIG_SIZE => self.common_config.read(
|
||||
o - COMMON_CONFIG_BAR_OFFSET,
|
||||
data,
|
||||
&mut self.queues,
|
||||
self.device.as_mut(),
|
||||
),
|
||||
o if ISR_CONFIG_BAR_OFFSET <= o && o < ISR_CONFIG_BAR_OFFSET + ISR_CONFIG_SIZE => {
|
||||
if let Some(v) = data.get_mut(0) {
|
||||
// Reading this register resets it to 0.
|
||||
*v = self.interrupt_status.swap(0, Ordering::SeqCst) as u8;
|
||||
}
|
||||
}
|
||||
o if DEVICE_CONFIG_BAR_OFFSET <= o
|
||||
&& o < DEVICE_CONFIG_BAR_OFFSET + DEVICE_CONFIG_SIZE =>
|
||||
{
|
||||
self.device.read_config(o - DEVICE_CONFIG_BAR_OFFSET, data);
|
||||
}
|
||||
o if NOTIFICATION_BAR_OFFSET <= o
|
||||
&& o < NOTIFICATION_BAR_OFFSET + NOTIFICATION_SIZE =>
|
||||
{
|
||||
// Handled with ioeventfds.
|
||||
}
|
||||
_ => (),
|
||||
}
|
||||
}
|
||||
|
||||
fn write_bar(&mut self, addr: u64, data: &[u8]) {
|
||||
let bar0 = u64::from(self.configuration.get_bar_addr(self.settings_bar as usize));
|
||||
let offset = addr - bar0;
|
||||
match offset {
|
||||
o if o < COMMON_CONFIG_BAR_OFFSET + COMMON_CONFIG_SIZE => self.common_config.write(
|
||||
o - COMMON_CONFIG_BAR_OFFSET,
|
||||
data,
|
||||
&mut self.queues,
|
||||
self.device.as_mut(),
|
||||
),
|
||||
o if ISR_CONFIG_BAR_OFFSET <= o && o < ISR_CONFIG_BAR_OFFSET + ISR_CONFIG_SIZE => {
|
||||
if let Some(v) = data.get(0) {
|
||||
self.interrupt_status
|
||||
.fetch_and(!(*v as usize), Ordering::SeqCst);
|
||||
}
|
||||
}
|
||||
o if DEVICE_CONFIG_BAR_OFFSET <= o
|
||||
&& o < DEVICE_CONFIG_BAR_OFFSET + DEVICE_CONFIG_SIZE =>
|
||||
{
|
||||
self.device.write_config(o - DEVICE_CONFIG_BAR_OFFSET, data);
|
||||
}
|
||||
o if NOTIFICATION_BAR_OFFSET <= o
|
||||
&& o < NOTIFICATION_BAR_OFFSET + NOTIFICATION_SIZE =>
|
||||
{
|
||||
// Handled with ioeventfds.
|
||||
}
|
||||
_ => (),
|
||||
};
|
||||
|
||||
if !self.device_activated && self.is_driver_ready() && self.are_queues_valid() {
|
||||
if let Some(interrupt_evt) = self.interrupt_evt.take() {
|
||||
if let Some(mem) = self.memory.take() {
|
||||
self.device
|
||||
.activate(
|
||||
mem,
|
||||
interrupt_evt,
|
||||
self.interrupt_status.clone(),
|
||||
self.queues.clone(),
|
||||
self.queue_evts.split_off(0),
|
||||
)
|
||||
.expect("Failed to activate device");;
|
||||
self.device_activated = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl BusDevice for VirtioPciDevice {
|
||||
fn read(&mut self, offset: u64, data: &mut [u8]) {
|
||||
self.read_bar(offset, data)
|
||||
}
|
||||
|
||||
fn write(&mut self, offset: u64, data: &[u8]) {
|
||||
self.write_bar(offset, data)
|
||||
}
|
||||
|
||||
fn write_config_register(&mut self, reg_idx: usize, offset: u64, data: &[u8]) {
|
||||
if offset as usize + data.len() > 4 {
|
||||
return;
|
||||
}
|
||||
|
||||
let regs = self.config_registers_mut();
|
||||
|
||||
match data.len() {
|
||||
1 => regs.write_byte(reg_idx * 4 + offset as usize, data[0]),
|
||||
2 => regs.write_word(
|
||||
reg_idx * 4 + offset as usize,
|
||||
u16::from(data[0]) | (u16::from(data[1]) << 8),
|
||||
),
|
||||
4 => regs.write_reg(reg_idx, LittleEndian::read_u32(data)),
|
||||
_ => (),
|
||||
}
|
||||
}
|
||||
|
||||
fn read_config_register(&self, reg_idx: usize) -> u32 {
|
||||
self.config_registers().read_reg(reg_idx)
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user