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hypervisor: Set pc and a1 for all vcpu

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It turns out we need to setup `a0`, `pc` and `a1` for all vcpus before
we run them, remove predicates used to set `pc` and `a1` for `vcpu0`.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
This commit is contained in:
Ruoqing He 2024-11-29 16:35:57 +08:00 committed by Rob Bradford
parent 9006013c60
commit c4063d26be
1 changed files with 22 additions and 26 deletions
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48
hypervisor/src/kvm/mod.rs
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@ -2731,33 +2731,29 @@ impl cpu::Vcpu for KvmVcpu {
) )
.map_err(|e| cpu::HypervisorCpuError::SetRiscvCoreRegister(e.into()))?; .map_err(|e| cpu::HypervisorCpuError::SetRiscvCoreRegister(e.into()))?;
// Other vCPUs are powered off initially awaiting wakeup. // Setting the PC (Processor Counter) to the current program address (kernel address).
if cpu_id == 0 { let pc = offset_of!(kvm_riscv_core, regs, user_regs_struct, pc);
// Setting the PC (Processor Counter) to the current program address (kernel address). self.fd
let pc = offset_of!(kvm_riscv_core, regs, user_regs_struct, pc); .lock()
self.fd .unwrap()
.lock() .set_one_reg(
.unwrap() riscv64_reg_id!(KVM_REG_RISCV_CORE, pc),
.set_one_reg( &boot_ip.to_le_bytes(),
riscv64_reg_id!(KVM_REG_RISCV_CORE, pc), )
&boot_ip.to_le_bytes(), .map_err(|e| cpu::HypervisorCpuError::SetRiscvCoreRegister(e.into()))?;
)
.map_err(|e| cpu::HypervisorCpuError::SetRiscvCoreRegister(e.into()))?;
// Last mandatory thing to set -> the address pointing to the FDT (also called DTB). // Last mandatory thing to set -> the address pointing to the FDT (also called DTB).
// "The device tree blob (dtb) must be placed on an 8-byte boundary and must // "The device tree blob (dtb) must be placed on an 8-byte boundary and must
// not exceed 2 megabytes in size." -> https://www.kernel.org/doc/Documentation/arch/riscv/boot.txt. // not exceed 64 kilobytes in size." -> https://www.kernel.org/doc/Documentation/arch/riscv/boot.txt.
// We are choosing to place it the end of DRAM. See `get_fdt_addr`. let a1 = offset_of!(kvm_riscv_core, regs, user_regs_struct, a1);
let a1 = offset_of!(kvm_riscv_core, regs, user_regs_struct, a1); self.fd
self.fd .lock()
.lock() .unwrap()
.unwrap() .set_one_reg(
.set_one_reg( riscv64_reg_id!(KVM_REG_RISCV_CORE, a1),
riscv64_reg_id!(KVM_REG_RISCV_CORE, a1), &fdt_start.to_le_bytes(),
&fdt_start.to_le_bytes(), )
) .map_err(|e| cpu::HypervisorCpuError::SetRiscvCoreRegister(e.into()))?;
.map_err(|e| cpu::HypervisorCpuError::SetRiscvCoreRegister(e.into()))?;
}
Ok(()) Ok(())
} }