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vmm: cpu: x86: Enable MTRR feature in CPUID

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The MTRR feature was missing from the CPUID, which is causing the guest
to ignore the MTRR settings exposed through dedicated MSRs.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
This commit is contained in:
Sebastien Boeuf 2020-09-25 14:19:03 +02:00
parent f4ec915c5d
commit c85e396ce5
1 changed files with 13 additions and 0 deletions
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13
vmm/src/cpu.rs
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@ -59,6 +59,8 @@ use vmm_sys_util::signal::{register_signal_handler, SIGRTMIN};
const TSC_DEADLINE_TIMER_ECX_BIT: u8 = 24; // tsc deadline timer ecx bit.
#[cfg(target_arch = "x86_64")]
const HYPERVISOR_ECX_BIT: u8 = 31; // Hypervisor ecx bit.
#[cfg(target_arch = "x86_64")]
const MTRR_EDX_BIT: u8 = 12; // Hypervisor ecx bit.
// Debug I/O port
#[cfg(target_arch = "x86_64")]
@ -742,6 +744,17 @@ impl CpuManager {
edx_bit: None,
});
// Enable MTRR feature
cpuid_patches.push(CpuidPatch {
function: 1,
index: 0,
flags_bit: None,
eax_bit: None,
ebx_bit: None,
ecx_bit: None,
edx_bit: Some(MTRR_EDX_BIT),
});
// Supported CPUID
let mut cpuid = hypervisor
.get_cpuid()