From d180deb679028dca8840515a6d216fac4874fcb7 Mon Sep 17 00:00:00 2001 From: Sebastien Boeuf Date: Tue, 6 Aug 2019 14:23:56 -0700 Subject: [PATCH] vm-virtio: pci: Fix PCI capability length The length of the PCI capability as it is being calculated by the guest was not accurate since it was not including the implicit 2 bytes offset. The reason for this offset is that the structure itself does not contain the capability ID (1 byte) and the next capability pointer (1 byte), but the structure exposed through PCI config space does include those bytes. Signed-off-by: Sebastien Boeuf --- vm-virtio/src/transport/pci_device.rs | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/vm-virtio/src/transport/pci_device.rs b/vm-virtio/src/transport/pci_device.rs index 6f6e43e78..3c717a176 100755 --- a/vm-virtio/src/transport/pci_device.rs +++ b/vm-virtio/src/transport/pci_device.rs @@ -68,12 +68,12 @@ impl PciCapability for VirtioPciCap { } } -const VIRTIO_PCI_CAPABILITY_BYTES: u8 = 16; +const VIRTIO_PCI_CAP_LEN_OFFSET: u8 = 2; impl VirtioPciCap { pub fn new(cfg_type: PciCapabilityType, pci_bar: u8, offset: u32, length: u32) -> Self { VirtioPciCap { - cap_len: VIRTIO_PCI_CAPABILITY_BYTES, + cap_len: (std::mem::size_of::() as u8) + VIRTIO_PCI_CAP_LEN_OFFSET, cfg_type: cfg_type as u8, pci_bar, padding: [0; 3], @@ -113,7 +113,8 @@ impl VirtioPciNotifyCap { ) -> Self { VirtioPciNotifyCap { cap: VirtioPciCap { - cap_len: std::mem::size_of::() as u8, + cap_len: (std::mem::size_of::() as u8) + + VIRTIO_PCI_CAP_LEN_OFFSET, cfg_type: cfg_type as u8, pci_bar, padding: [0; 3],