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pci: Only allow writes to RW bits in MSI-X register

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The PCI spec specifies that only the following bits are writable:

16: MSI Enable
20,21,22: Multiple Message Enable
26: Extended Message Data Enable

Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Rob Bradford 2022-02-16 17:23:57 +00:00
parent 42b5d4a2f7
commit d9eff12ba3
1 changed files with 2 additions and 0 deletions
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2
pci/src/configuration.rs
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@ -21,6 +21,7 @@ const ROM_BAR_REG: usize = 12;
const BAR_IO_ADDR_MASK: u32 = 0xffff_fffc;
const BAR_MEM_ADDR_MASK: u32 = 0xffff_fff0;
const ROM_BAR_ADDR_MASK: u32 = 0xffff_f800;
const MSIX_REGISTER_MASK: u32 = 0x471_0000;
const NUM_BAR_REGS: usize = 6;
const CAPABILITY_LIST_HEAD_OFFSET: usize = 0x34;
const FIRST_CAPABILITY_OFFSET: usize = 0x40;
@ -716,6 +717,7 @@ impl PciConfiguration {
if cap_data.id() == PciCapabilityId::MsiX {
self.msix_cap_reg_idx = Some(cap_offset / 4);
self.writable_bits[self.msix_cap_reg_idx.unwrap()] = MSIX_REGISTER_MASK;
}
Ok(cap_offset)