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pci: Only allow writes to RW bits in MSI-X register
The PCI spec specifies that only the following bits are writable: 16: MSI Enable 20,21,22: Multiple Message Enable 26: Extended Message Data Enable Signed-off-by: Rob Bradford <robert.bradford@intel.com>
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@ -21,6 +21,7 @@ const ROM_BAR_REG: usize = 12;
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const BAR_IO_ADDR_MASK: u32 = 0xffff_fffc;
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const BAR_IO_ADDR_MASK: u32 = 0xffff_fffc;
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const BAR_MEM_ADDR_MASK: u32 = 0xffff_fff0;
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const BAR_MEM_ADDR_MASK: u32 = 0xffff_fff0;
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const ROM_BAR_ADDR_MASK: u32 = 0xffff_f800;
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const ROM_BAR_ADDR_MASK: u32 = 0xffff_f800;
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const MSIX_REGISTER_MASK: u32 = 0x471_0000;
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const NUM_BAR_REGS: usize = 6;
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const NUM_BAR_REGS: usize = 6;
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const CAPABILITY_LIST_HEAD_OFFSET: usize = 0x34;
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const CAPABILITY_LIST_HEAD_OFFSET: usize = 0x34;
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const FIRST_CAPABILITY_OFFSET: usize = 0x40;
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const FIRST_CAPABILITY_OFFSET: usize = 0x40;
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@ -716,6 +717,7 @@ impl PciConfiguration {
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if cap_data.id() == PciCapabilityId::MsiX {
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if cap_data.id() == PciCapabilityId::MsiX {
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self.msix_cap_reg_idx = Some(cap_offset / 4);
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self.msix_cap_reg_idx = Some(cap_offset / 4);
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self.writable_bits[self.msix_cap_reg_idx.unwrap()] = MSIX_REGISTER_MASK;
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}
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}
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Ok(cap_offset)
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Ok(cap_offset)
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