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vmm: Rename PCI_MMIO_CONFIG_SIZE and move it to arch

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The constant `PCI_MMIO_CONFIG_SIZE` defined in `vmm/pci_segment.rs`
describes the MMIO configuation size for each PCI segment. However,
this name conflicts with the `PCI_MMCONFIG_SIZE` defined in `layout.rs`
in the `arch` crate, which describes the memory size of the PCI MMIO
configuration region.

Therefore, this commit renames the `PCI_MMIO_CONFIG_SIZE` to
`PCI_MMIO_CONFIG_SIZE_PER_SEGMENT` and moves this constant from `vmm`
crate to `arch` crate.

Signed-off-by: Henry Wang <Henry.Wang@arm.com>
(cherry picked from commit 2f8540da70)
Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Henry Wang 2021-11-25 21:53:59 -05:00 committed by Rob Bradford
parent 42c0b4055a
commit dc858ed96f
3 changed files with 9 additions and 7 deletions
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2
arch/src/aarch64/layout.rs
View File

@ -82,6 +82,8 @@ pub const MEM_32BIT_DEVICES_SIZE: u64 = 0x2000_0000;
/// PCI MMCONFIG space (start: after the device space at 1 GiB, length: 256MiB)
pub const PCI_MMCONFIG_START: GuestAddress = GuestAddress(0x3000_0000);
pub const PCI_MMCONFIG_SIZE: u64 = 256 << 20;
// One bus with potentially 256 devices (32 slots x 8 functions).
pub const PCI_MMIO_CONFIG_SIZE_PER_SEGMENT: u64 = 4096 * 256;
/// Start of RAM on 64 bit ARM.
pub const RAM_64BIT_START: u64 = 0x4000_0000;

2
arch/src/x86_64/layout.rs
View File

@ -93,6 +93,8 @@ pub const MEM_32BIT_DEVICES_SIZE: u64 = 640 << 20;
pub const PCI_MMCONFIG_START: GuestAddress =
GuestAddress(MEM_32BIT_DEVICES_START.0 + MEM_32BIT_DEVICES_SIZE);
pub const PCI_MMCONFIG_SIZE: u64 = 256 << 20;
// One bus with potentially 256 devices (32 slots x 8 functions).
pub const PCI_MMIO_CONFIG_SIZE_PER_SEGMENT: u64 = 4096 * 256;
// TSS is 3 pages after the PCI MMCONFIG space
pub const KVM_TSS_START: GuestAddress = GuestAddress(PCI_MMCONFIG_START.0 + PCI_MMCONFIG_SIZE);

12
vmm/src/pci_segment.rs
View File

@ -22,9 +22,6 @@ use uuid::Uuid;
use vm_allocator::AddressAllocator;
use vm_device::BusDevice;
// One bus with potentially 256 devices (32 slots x 8 functions).
const PCI_MMIO_CONFIG_SIZE: u64 = 4096 * 256;
pub(crate) struct PciSegment {
pub(crate) id: u16,
pub(crate) pci_bus: Arc<Mutex<PciBus>>,
@ -62,14 +59,15 @@ impl PciSegment {
)));
let pci_config_mmio = Arc::new(Mutex::new(PciConfigMmio::new(Arc::clone(&pci_bus))));
let mmio_config_address = layout::PCI_MMCONFIG_START.0 + PCI_MMIO_CONFIG_SIZE * id as u64;
let mmio_config_address =
layout::PCI_MMCONFIG_START.0 + layout::PCI_MMIO_CONFIG_SIZE_PER_SEGMENT * id as u64;
address_manager
.mmio_bus
.insert(
Arc::clone(&pci_config_mmio) as Arc<Mutex<dyn BusDevice>>,
mmio_config_address,
PCI_MMIO_CONFIG_SIZE,
layout::PCI_MMIO_CONFIG_SIZE_PER_SEGMENT,
)
.map_err(DeviceManagerError::BusError)?;
@ -363,7 +361,7 @@ impl Aml for PciSegment {
&aml::Memory32Fixed::new(
true,
self.mmio_config_address as u32,
PCI_MMIO_CONFIG_SIZE as u32,
layout::PCI_MMIO_CONFIG_SIZE_PER_SEGMENT as u32,
),
&aml::AddressSpace::new_memory(
aml::AddressSpaceCachable::NotCacheable,
@ -392,7 +390,7 @@ impl Aml for PciSegment {
&aml::Memory32Fixed::new(
true,
self.mmio_config_address as u32,
PCI_MMIO_CONFIG_SIZE as u32,
layout::PCI_MMIO_CONFIG_SIZE_PER_SEGMENT as u32,
),
&aml::AddressSpace::new_memory(
aml::AddressSpaceCachable::NotCacheable,