From ecb66b5e9460029d39d8a4a7a5143699b32ca574 Mon Sep 17 00:00:00 2001
From: Michael Zhao <michael.zhao@arm.com>
Date: Tue, 26 Jul 2022 14:19:03 +0800
Subject: [PATCH] arch: Declare system registers on AArch64

Signed-off-by: Michael Zhao <michael.zhao@arm.com>
---
 arch/src/aarch64/mod.rs  |  2 ++
 arch/src/aarch64/regs.rs | 41 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)
 create mode 100644 arch/src/aarch64/regs.rs

diff --git a/arch/src/aarch64/mod.rs b/arch/src/aarch64/mod.rs
index bf71ac080..0f4194d1c 100644
--- a/arch/src/aarch64/mod.rs
+++ b/arch/src/aarch64/mod.rs
@@ -6,6 +6,8 @@
 pub mod fdt;
 /// Layout for this aarch64 system.
 pub mod layout;
+/// Module for system registers definition
+pub mod regs;
 /// Module for loading UEFI binary.
 pub mod uefi;
 
diff --git a/arch/src/aarch64/regs.rs b/arch/src/aarch64/regs.rs
new file mode 100644
index 000000000..696069320
--- /dev/null
+++ b/arch/src/aarch64/regs.rs
@@ -0,0 +1,41 @@
+// Copyright 2022 Arm Limited (or its affiliates). All rights reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+///
+/// AArch64 system register encoding:
+/// See https://developer.arm.com/documentation/ddi0487 (chapter D12)
+///
+///   31      22  21 20 19 18 16 15 12 11  8 7   5 4  0
+///  +----------+---+-----+-----+-----+-----+-----+----+
+///  |1101010100| L | op0 | op1 | CRn | CRm | op2 | Rt |
+///  +----------+---+-----+-----+-----+-----+-----+----+
+///
+/// Notes:
+/// - L and Rt are reserved as implementation defined fields, ignored.
+///
+const SYSREG_HEAD: u32 = 0b1101010100u32 << 22;
+const SYSREG_OP0_SHIFT: u32 = 19;
+const SYSREG_OP0_MASK: u32 = 0b11u32 << 19;
+const SYSREG_OP1_SHIFT: u32 = 16;
+const SYSREG_OP1_MASK: u32 = 0b111u32 << 16;
+const SYSREG_CRN_SHIFT: u32 = 12;
+const SYSREG_CRN_MASK: u32 = 0b1111u32 << 12;
+const SYSREG_CRM_SHIFT: u32 = 8;
+const SYSREG_CRM_MASK: u32 = 0b1111u32 << 8;
+const SYSREG_OP2_SHIFT: u32 = 5;
+const SYSREG_OP2_MASK: u32 = 0b111u32 << 5;
+
+/// Define the ID of system registers
+#[macro_export]
+macro_rules! arm64_sys_reg {
+    ($name: tt, $op0: tt, $op1: tt, $crn: tt, $crm: tt, $op2: tt) => {
+        pub const $name: u32 = SYSREG_HEAD
+            | ((($op0 as u32) << SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK as u32)
+            | ((($op1 as u32) << SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK as u32)
+            | ((($crn as u32) << SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK as u32)
+            | ((($crm as u32) << SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK as u32)
+            | ((($op2 as u32) << SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK as u32);
+    };
+}
+
+arm64_sys_reg!(MPIDR_EL1, 3, 0, 0, 0, 5);