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misc: Remove unnecessary literal casts

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Signed-off-by: Rob Bradford <robert.bradford@intel.com>
This commit is contained in:
Rob Bradford 2021-01-02 20:37:31 +00:00 committed by Sebastien Boeuf
parent 05cdef17f4
commit fabd63072b
8 changed files with 21 additions and 21 deletions
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4
arch/src/x86_64/mod.rs
View File

@ -974,7 +974,7 @@ mod tests {
#[test]
fn regions_lt_4gb() {
let regions = arch_memory_regions(1 << 29 as GuestUsize);
let regions = arch_memory_regions(1 << 29);
assert_eq!(3, regions.len());
assert_eq!(GuestAddress(0), regions[0].0);
assert_eq!(1usize << 29, regions[0].1);
@ -982,7 +982,7 @@ mod tests {
#[test]
fn regions_gt_4gb() {
let regions = arch_memory_regions((1 << 32 as GuestUsize) + 0x8000);
let regions = arch_memory_regions((1 << 32) + 0x8000);
assert_eq!(4, regions.len());
assert_eq!(GuestAddress(0), regions[0].0);
assert_eq!(GuestAddress(1 << 32), regions[1].0);

2
devices/src/ioapic.rs
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@ -193,7 +193,7 @@ impl Ioapic {
) -> Result<Ioapic> {
let interrupt_source_group = interrupt_manager
.create_group(MsiIrqGroupConfig {
base: 0 as InterruptIndex,
base: 0,
count: NUM_IOAPIC_PINS as InterruptIndex,
})
.map_err(Error::CreateInterruptSourceGroup)?;

18
devices/src/legacy/serial.rs
View File

@ -474,13 +474,13 @@ mod tests {
Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
);
serial.write(0, LCR as u64, &[LCR_DLAB_BIT as u8]);
serial.write(0, DLAB_LOW as u64, &[0x12 as u8]);
serial.write(0, DLAB_HIGH as u64, &[0x34 as u8]);
serial.write(0, LCR as u64, &[LCR_DLAB_BIT]);
serial.write(0, DLAB_LOW as u64, &[0x12]);
serial.write(0, DLAB_HIGH as u64, &[0x34]);
let mut data = [0u8];
serial.read(0, LCR as u64, &mut data[..]);
assert_eq!(data[0], LCR_DLAB_BIT as u8);
assert_eq!(data[0], LCR_DLAB_BIT);
serial.read(0, DLAB_LOW as u64, &mut data[..]);
assert_eq!(data[0], 0x12);
serial.read(0, DLAB_HIGH as u64, &mut data[..]);
@ -495,16 +495,16 @@ mod tests {
Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
);
serial.write(0, MCR as u64, &[MCR_LOOP_BIT as u8]);
serial.write(0, MCR as u64, &[MCR_LOOP_BIT]);
serial.write(0, DATA as u64, &[b'a']);
serial.write(0, DATA as u64, &[b'b']);
serial.write(0, DATA as u64, &[b'c']);
let mut data = [0u8];
serial.read(0, MSR as u64, &mut data[..]);
assert_eq!(data[0], DEFAULT_MODEM_STATUS as u8);
assert_eq!(data[0], DEFAULT_MODEM_STATUS);
serial.read(0, MCR as u64, &mut data[..]);
assert_eq!(data[0], MCR_LOOP_BIT as u8);
assert_eq!(data[0], MCR_LOOP_BIT);
serial.read(0, DATA as u64, &mut data[..]);
assert_eq!(data[0], b'a');
serial.read(0, DATA as u64, &mut data[..]);
@ -521,10 +521,10 @@ mod tests {
Arc::new(Box::new(TestInterrupt::new(intr_evt.try_clone().unwrap()))),
);
serial.write(0, SCR as u64, &[0x12 as u8]);
serial.write(0, SCR as u64, &[0x12]);
let mut data = [0u8];
serial.read(0, SCR as u64, &mut data[..]);
assert_eq!(data[0], 0x12 as u8);
assert_eq!(data[0], 0x12);
}
}

4
hypervisor/src/arch/x86/emulator/instructions/mov.rs
View File

@ -508,7 +508,7 @@ mod tests {
// Only run the first instruction.
assert!(vmm.emulate_first_insn(cpu_id, &insn).is_ok());
assert_eq!(ip + 7 as u64, vmm.cpu_state(cpu_id).unwrap().ip());
assert_eq!(ip + 7, vmm.cpu_state(cpu_id).unwrap().ip());
let new_rax: u64 = vmm
.cpu_state(cpu_id)
@ -541,7 +541,7 @@ mod tests {
// Run the 2 first instructions.
assert!(vmm.emulate_insn(cpu_id, &insn, Some(2)).is_ok());
assert_eq!(ip + 7 + 4 as u64, vmm.cpu_state(cpu_id).unwrap().ip());
assert_eq!(ip + 7 + 4, vmm.cpu_state(cpu_id).unwrap().ip());
let rbx: u64 = vmm
.cpu_state(cpu_id)

6
hypervisor/src/mshv/mod.rs
View File

@ -307,7 +307,7 @@ impl hypervisor::Hypervisor for MshvHypervisor {
/// Get the supported CpuID
///
fn get_cpuid(&self) -> hypervisor::Result<CpuId> {
Ok(CpuId::new(1 as usize))
Ok(CpuId::new(1))
}
#[cfg(target_arch = "x86_64")]
///
@ -601,7 +601,7 @@ impl cpu::Vcpu for MshvVcpu {
}
hv_message_type_HVMSG_X64_MSR_INTERCEPT => {
let info = x.to_msr_info().unwrap();
if info.header.intercept_access_type == 0 as u8 {
if info.header.intercept_access_type == 0 {
debug!("msr read: {:x}", info.msr_number);
} else {
debug!("msr write: {:x}", info.msr_number);
@ -935,7 +935,7 @@ impl vm::Vm for MshvVm {
let vcpu = MshvVcpu {
fd: vcpu_fd,
vp_index: id,
cpuid: CpuId::new(1 as usize),
cpuid: CpuId::new(1),
msrs: self.msrs.clone(),
ioeventfds: self.ioeventfds.clone(),
gsi_routes: self.gsi_routes.clone(),

2
virtio-devices/src/vhost_user/fs.rs
View File

@ -128,7 +128,7 @@ impl VhostUserMasterReqHandler for SlaveReqHandler {
libc::PROT_NONE,
libc::MAP_ANONYMOUS | libc::MAP_PRIVATE | libc::MAP_FIXED,
-1,
0 as libc::off_t,
0,
)
};
if ret == libc::MAP_FAILED {

2
vm-virtio/src/queue.rs
View File

@ -1051,7 +1051,7 @@ pub mod tests {
assert!(c.is_indirect());
// create an indirect table with 4 chained descriptors
let mut indirect_table = Vec::with_capacity(4 as usize);
let mut indirect_table = Vec::with_capacity(4);
for j in 0..4 {
let desc = VirtqDesc::new(GuestAddress(0x1000 + (j * 16)), m);
desc.set(0x1000, 0x1000, VIRTQ_DESC_F_NEXT, (j + 1) as u16);

4
vmm/src/memory_manager.rs
View File

@ -699,7 +699,7 @@ impl MemoryManager {
},
#[cfg(target_arch = "x86_64")]
{
1 << 16 as GuestUsize
1 << 16
},
GuestAddress(0),
mmio_address_space_size,
@ -1370,7 +1370,7 @@ impl MemoryManager {
prot,
flags,
file.as_raw_fd(),
0 as libc::off_t,
0,
)
} as u64;