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hypervisor: x86: Add a minimal CpuStateManager implementation
Minimal will be defined by the amount of emulated instructions. Carrying all GPRs, all CRs, segment registers and table registers should cover quite a few instructions. Co-developed-by: Wei Liu <liuwe@microsoft.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
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@ -7,7 +7,7 @@
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extern crate iced_x86;
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extern crate iced_x86;
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use crate::arch::emulator::PlatformError;
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use crate::arch::emulator::PlatformError;
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use crate::x86_64::SegmentRegister;
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use crate::x86_64::{SegmentRegister, SpecialRegisters, StandardRegisters};
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use iced_x86::*;
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use iced_x86::*;
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/// CpuStateManager manages an x86 CPU state.
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/// CpuStateManager manages an x86 CPU state.
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@ -84,3 +84,261 @@ pub trait CpuStateManager: Clone {
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/// * `flags` - The CPU flags
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/// * `flags` - The CPU flags
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fn set_flags(&mut self, flags: u64);
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fn set_flags(&mut self, flags: u64);
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}
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}
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const REGISTER_MASK_64: u64 = 0xffff_ffff_ffff_ffffu64;
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const REGISTER_MASK_32: u64 = 0xffff_ffffu64;
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const REGISTER_MASK_16: u64 = 0xffffu64;
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const REGISTER_MASK_8: u64 = 0xffu64;
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macro_rules! set_reg {
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($reg:expr, $mask:expr, $value:expr) => {
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$reg = ($reg & $mask) | $value
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};
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}
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#[derive(Clone, Default, Debug)]
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/// A minimal, emulated CPU state.
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///
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/// Hypervisors needing x86 emulation can choose to either use their own
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/// CPU state structures and implement the CpuStateManager interface for it,
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/// or use `EmulatorCpuState`. The latter implies creating a new state
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/// `EmulatorCpuState` instance for each platform `cpu_state()` call, which
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/// might be less efficient.
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pub struct EmulatorCpuState {
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pub regs: StandardRegisters,
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pub sregs: SpecialRegisters,
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}
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impl CpuStateManager for EmulatorCpuState {
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fn read_reg(&self, reg: Register) -> Result<u64, PlatformError> {
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let mut reg_value: u64 = match reg {
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Register::RAX | Register::EAX | Register::AX | Register::AL | Register::AH => {
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self.regs.rax
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}
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Register::RBX | Register::EBX | Register::BX | Register::BL | Register::BH => {
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self.regs.rbx
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}
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Register::RCX | Register::ECX | Register::CX | Register::CL | Register::CH => {
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self.regs.rcx
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}
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Register::RDX | Register::EDX | Register::DX | Register::DL | Register::DH => {
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self.regs.rdx
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}
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Register::RSP | Register::ESP => self.regs.rsp,
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Register::RBP | Register::EBP => self.regs.rbp,
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Register::RSI | Register::ESI => self.regs.rsi,
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Register::RDI | Register::EDI | Register::DI | Register::DIL => self.regs.rdi,
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Register::R8 | Register::R8D => self.regs.r8,
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Register::R9 | Register::R9D => self.regs.r9,
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Register::R10 | Register::R10D => self.regs.r10,
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Register::R11 | Register::R11D => self.regs.r11,
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Register::R12 | Register::R12D => self.regs.r12,
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Register::R13 | Register::R13D => self.regs.r13,
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Register::R14 | Register::R14D => self.regs.r14,
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Register::R15 | Register::R15D => self.regs.r15,
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Register::CR0 => self.sregs.cr0,
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Register::CR2 => self.sregs.cr2,
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Register::CR3 => self.sregs.cr3,
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Register::CR4 => self.sregs.cr4,
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Register::CR8 => self.sregs.cr8,
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r => {
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return Err(PlatformError::InvalidRegister(anyhow!(
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"read_reg invalid GPR {:?}",
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r
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)))
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}
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};
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reg_value = if reg.is_gpr64() || reg.is_cr() {
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reg_value
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} else if reg.is_gpr32() {
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reg_value & REGISTER_MASK_32
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} else if reg.is_gpr16() {
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reg_value & REGISTER_MASK_16
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} else if reg.is_gpr8() {
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if reg == Register::AH
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|| reg == Register::BH
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|| reg == Register::CH
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|| reg == Register::DH
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{
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(reg_value >> 8) & REGISTER_MASK_8
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} else {
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reg_value & REGISTER_MASK_8
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}
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} else {
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return Err(PlatformError::InvalidRegister(anyhow!(
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"read_reg invalid GPR {:?}",
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reg
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)));
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};
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debug!("Register read: {:#x} from {:?}", reg_value, reg);
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Ok(reg_value)
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}
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fn write_reg(&mut self, reg: Register, val: u64) -> Result<(), PlatformError> {
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debug!("Register write: {:#x} to {:?}", val, reg);
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// SDM Vol 1 - 3.4.1.1
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//
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// 8-bit and 16-bit operands generate an 8-bit or 16-bit result.
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// The upper 56 bits or 48 bits (respectively) of the destination
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// general-purpose register are not modified by the operation.
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let (reg_value, mask): (u64, u64) = if reg.is_gpr64() || reg.is_cr() {
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(val, !REGISTER_MASK_64)
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} else if reg.is_gpr32() {
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(val & REGISTER_MASK_32, !REGISTER_MASK_64)
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} else if reg.is_gpr16() {
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(val & REGISTER_MASK_16, !REGISTER_MASK_16)
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} else if reg.is_gpr8() {
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if reg == Register::AH
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|| reg == Register::BH
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|| reg == Register::CH
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|| reg == Register::DH
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{
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((val & REGISTER_MASK_8) << 8, !(REGISTER_MASK_8 << 8))
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} else {
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(val & REGISTER_MASK_8, !REGISTER_MASK_8)
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}
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} else {
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return Err(PlatformError::InvalidRegister(anyhow!(
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"write_reg invalid register {:?}",
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reg
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)));
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};
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match reg {
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Register::RAX | Register::EAX | Register::AX | Register::AL | Register::AH => {
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set_reg!(self.regs.rax, mask, reg_value);
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}
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Register::RBX | Register::EBX | Register::BX | Register::BL | Register::BH => {
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set_reg!(self.regs.rbx, mask, reg_value);
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}
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Register::RCX | Register::ECX | Register::CX | Register::CL | Register::CH => {
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set_reg!(self.regs.rcx, mask, reg_value);
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}
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Register::RDX | Register::EDX | Register::DX | Register::DL | Register::DH => {
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set_reg!(self.regs.rdx, mask, reg_value);
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}
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Register::RSP | Register::ESP => {
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set_reg!(self.regs.rsp, mask, reg_value)
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}
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Register::RBP | Register::EBP => {
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set_reg!(self.regs.rbp, mask, reg_value)
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}
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Register::RSI | Register::ESI => {
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set_reg!(self.regs.rsi, mask, reg_value)
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}
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Register::RDI | Register::EDI | Register::DI | Register::DIL => {
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set_reg!(self.regs.rdi, mask, reg_value)
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}
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Register::R8 | Register::R8D => {
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set_reg!(self.regs.r8, mask, reg_value)
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}
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Register::R9 | Register::R9D => {
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set_reg!(self.regs.r9, mask, reg_value)
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}
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Register::R10 | Register::R10D => {
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set_reg!(self.regs.r10, mask, reg_value)
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}
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Register::R11 | Register::R11D => {
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set_reg!(self.regs.r11, mask, reg_value)
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}
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Register::R12 | Register::R12D => {
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set_reg!(self.regs.r12, mask, reg_value)
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}
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Register::R13 | Register::R13D => {
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set_reg!(self.regs.r13, mask, reg_value)
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}
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Register::R14 | Register::R14D => {
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set_reg!(self.regs.r14, mask, reg_value)
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}
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Register::R15 | Register::R15D => {
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set_reg!(self.regs.r15, mask, reg_value)
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}
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Register::CR0 => set_reg!(self.sregs.cr0, mask, reg_value),
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Register::CR2 => set_reg!(self.sregs.cr2, mask, reg_value),
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Register::CR3 => set_reg!(self.sregs.cr3, mask, reg_value),
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Register::CR4 => set_reg!(self.sregs.cr4, mask, reg_value),
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Register::CR8 => set_reg!(self.sregs.cr8, mask, reg_value),
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_ => {
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return Err(PlatformError::InvalidRegister(anyhow!(
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"write_reg invalid register {:?}",
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reg
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)))
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}
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}
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Ok(())
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}
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fn read_segment(&self, reg: Register) -> Result<SegmentRegister, PlatformError> {
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if !reg.is_segment_register() {
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return Err(PlatformError::InvalidRegister(anyhow!(
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"read_segment {:?} is not a segment register",
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reg
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)));
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}
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match reg {
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Register::CS => Ok(self.sregs.cs),
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Register::DS => Ok(self.sregs.ds),
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Register::ES => Ok(self.sregs.es),
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Register::FS => Ok(self.sregs.fs),
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Register::GS => Ok(self.sregs.gs),
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Register::SS => Ok(self.sregs.ss),
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r => Err(PlatformError::InvalidRegister(anyhow!(
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"read_segment invalid register {:?}",
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r
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))),
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}
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}
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fn write_segment(
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&mut self,
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reg: Register,
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segment_register: SegmentRegister,
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) -> Result<(), PlatformError> {
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if !reg.is_segment_register() {
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return Err(PlatformError::InvalidRegister(anyhow!("{:?}", reg)));
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}
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match reg {
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Register::CS => self.sregs.cs = segment_register,
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Register::DS => self.sregs.ds = segment_register,
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Register::ES => self.sregs.es = segment_register,
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Register::FS => self.sregs.fs = segment_register,
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Register::GS => self.sregs.gs = segment_register,
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Register::SS => self.sregs.ss = segment_register,
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r => return Err(PlatformError::InvalidRegister(anyhow!("{:?}", r))),
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}
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Ok(())
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}
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fn ip(&self) -> u64 {
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self.regs.rip
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}
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fn set_ip(&mut self, ip: u64) {
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self.regs.rip = ip;
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}
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fn efer(&self) -> u64 {
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self.sregs.efer
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}
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fn set_efer(&mut self, efer: u64) {
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self.sregs.efer = efer
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}
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fn flags(&self) -> u64 {
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self.regs.rflags
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}
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fn set_flags(&mut self, flags: u64) {
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self.regs.rflags = flags;
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}
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}
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