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2 Commits

Author SHA1 Message Date
Sebastien Boeuf
1379abb94b pci: msi: Fix MSG_CTL update through 32 bits write 
If the MSG_CTL is being written from a 32 bits write access, the offset
won't be 0x2, but 0x0 instead. That's simply because 32 bits access have
to be aligned on each double word.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
 2019-12-04 08:48:17 +01:00
Sebastien Boeuf
ee39e46568 pci: Add MSI capability structure 
In order to support use cases that require MSI, the pci crate is
being expanded with the description of an MSI PCI capability
structure through the new MsiCap Rust structure.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
 2019-07-22 09:50:10 -07:00