External/cloud-hypervisor
1
0
Fork 0
mirror of https://github.com/cloud-hypervisor/cloud-hypervisor.git synced 2024-11-09 05:10:07 +00:00
Code Issues Packages Projects Releases Wiki Activity
218 Commits 16 Branches 60 Tags 56 MiB
f86b9dd95e
Commit Graph

3 Commits

Author SHA1 Message Date
Sebastien Boeuf
1268165040 pci: Allow for registering IO and Memory BAR 
This patch adds the support for both IO and Memory BARs by expecting
the function allocate_bars() to identify the type of each BAR.
Based on the type, register_mapping() insert the address range on the
appropriate bus (PIO or MMIO).

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
 2019-07-22 09:50:10 -07:00
Samuel Ortiz
2b2c31d206 pci: Use device PCI header type for our root bridge 
The Bridge header type is really meant to be for PCI-to-PCI bridges.

Fixes: #85

Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
 2019-07-10 09:53:02 +02:00
Jing Liu
2bb0b22cc1 pci: Refine pci topology 
PciConfigIo is a legacy pci bus dispatcher, which manages all pci
devices including a pci root bridge. However, it is unnecessary to
design a complex hierarchy which redirects every access by PciRoot.

Since pci root bridge is also a pci device instance, and only contains
easy config space read/write, and PciConfigIo actually acts as a pci bus
to dispatch resource based resolving when VMExit, we re-arrange to make
the pci hierarchy clean.

Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
 2019-07-09 10:01:18 +02:00