// Copyright © 2019 Intel Corporation // // SPDX-License-Identifier: Apache-2.0 // use crate::cpu::CpuManager; use crate::device_manager::DeviceManager; use crate::memory_manager::MemoryManager; use acpi_tables::{ aml::Aml, rsdp::RSDP, sdt::{GenericAddress, SDT}, }; use arch::layout; use std::sync::{Arc, Mutex}; use vm_memory::{Address, ByteValued, Bytes, GuestAddress, GuestMemoryMmap, GuestMemoryRegion}; #[repr(packed)] #[derive(Default)] struct PCIRangeEntry { pub base_address: u64, pub segment: u16, pub start: u8, pub end: u8, _reserved: u32, } #[repr(packed)] #[derive(Default)] struct MemoryAffinity { pub type_: u8, pub length: u8, pub proximity_domain: u32, _reserved1: u16, pub base_addr_lo: u32, pub base_addr_hi: u32, pub length_lo: u32, pub length_hi: u32, _reserved2: u32, pub flags: u32, _reserved3: u64, } pub fn create_dsdt_table( device_manager: &Arc>, cpu_manager: &Arc>, memory_manager: &Arc>, ) -> SDT { // DSDT let mut dsdt = SDT::new(*b"DSDT", 36, 6, *b"CLOUDH", *b"CHDSDT ", 1); dsdt.append_slice(device_manager.lock().unwrap().to_aml_bytes().as_slice()); dsdt.append_slice(cpu_manager.lock().unwrap().to_aml_bytes().as_slice()); dsdt.append_slice(memory_manager.lock().unwrap().to_aml_bytes().as_slice()); dsdt } pub fn create_acpi_tables( guest_mem: &GuestMemoryMmap, device_manager: &Arc>, cpu_manager: &Arc>, memory_manager: &Arc>, ) -> GuestAddress { // RSDP is at the EBDA let rsdp_offset = layout::RSDP_POINTER; let mut tables: Vec = Vec::new(); // DSDT let dsdt = create_dsdt_table(device_manager, cpu_manager, memory_manager); let dsdt_offset = rsdp_offset.checked_add(RSDP::len() as u64).unwrap(); guest_mem .write_slice(dsdt.as_slice(), dsdt_offset) .expect("Error writing DSDT table"); // FACP aka FADT // Revision 6 of the ACPI FADT table is 276 bytes long let mut facp = SDT::new(*b"FACP", 276, 6, *b"CLOUDH", *b"CHFACP ", 1); // PM_TMR_BLK I/O port facp.write(76, 0xb008u32); // HW_REDUCED_ACPI, RESET_REG_SUP, TMR_VAL_EXT let fadt_flags: u32 = 1 << 20 | 1 << 10 | 1 << 8; facp.write(112, fadt_flags); // RESET_REG facp.write(116, GenericAddress::io_port_address::(0x3c0)); // RESET_VALUE facp.write(128, 1u8); facp.write(131, 3u8); // FADT minor version facp.write(140, dsdt_offset.0); // X_DSDT // X_PM_TMR_BLK facp.write(208, GenericAddress::io_port_address::(0xb008)); // SLEEP_CONTROL_REG facp.write(244, GenericAddress::io_port_address::(0x3c0)); // SLEEP_STATUS_REG facp.write(256, GenericAddress::io_port_address::(0x3c0)); facp.write(268, b"CLOUDHYP"); // Hypervisor Vendor Identity facp.update_checksum(); let facp_offset = dsdt_offset.checked_add(dsdt.len() as u64).unwrap(); guest_mem .write_slice(facp.as_slice(), facp_offset) .expect("Error writing FACP table"); tables.push(facp_offset.0); // MADT let madt = cpu_manager.lock().unwrap().create_madt(); let madt_offset = facp_offset.checked_add(facp.len() as u64).unwrap(); guest_mem .write_slice(madt.as_slice(), madt_offset) .expect("Error writing MADT table"); tables.push(madt_offset.0); // MCFG let mut mcfg = SDT::new(*b"MCFG", 36, 1, *b"CLOUDH", *b"CHMCFG ", 1); // MCFG reserved 8 bytes mcfg.append(0u64); // 32-bit PCI enhanced configuration mechanism mcfg.append(PCIRangeEntry { base_address: layout::PCI_MMCONFIG_START.0, segment: 0, start: 0, end: 0xff, ..Default::default() }); let mcfg_offset = madt_offset.checked_add(madt.len() as u64).unwrap(); guest_mem .write_slice(mcfg.as_slice(), mcfg_offset) .expect("Error writing MCFG table"); tables.push(mcfg_offset.0); // SRAT // Only created if the NUMA nodes list is not empty. let numa_nodes = memory_manager.lock().unwrap().numa_nodes().clone(); let (prev_tbl_len, prev_tbl_off) = if numa_nodes.is_empty() { (mcfg.len(), mcfg_offset) } else { let mut srat = SDT::new(*b"SRAT", 36, 3, *b"CLOUDH", *b"CHSRAT ", 1); // SRAT reserved 12 bytes srat.append_slice(&[0u8; 12]); // Check the MemoryAffinity structure is the right size as expected by // the ACPI specification. assert_eq!(std::mem::size_of::(), 40); for (node_id, node) in numa_nodes.iter() { for region in node.memory_regions() { let proximity_domain = *node_id as u32; let base_addr = region.start_addr().raw_value(); let base_addr_lo = (base_addr & 0xffff_ffff) as u32; let base_addr_hi = (base_addr >> 32) as u32; let length = region.len() as u64; let length_lo = (length & 0xffff_ffff) as u32; let length_hi = (length >> 32) as u32; // Flags // - Enabled = 1 (bit 0) // - Hot Pluggable = 0 (bit 1) // - NonVolatile = 0 (bit 2) // - Reserved bits 3-31 let flags = 1; srat.append(MemoryAffinity { type_: 1, length: 40, proximity_domain, base_addr_lo, base_addr_hi, length_lo, length_hi, flags, ..Default::default() }); } } let srat_offset = mcfg_offset.checked_add(mcfg.len() as u64).unwrap(); guest_mem .write_slice(srat.as_slice(), srat_offset) .expect("Error writing SRAT table"); tables.push(srat_offset.0); (srat.len(), srat_offset) }; // XSDT let mut xsdt = SDT::new(*b"XSDT", 36, 1, *b"CLOUDH", *b"CHXSDT ", 1); for table in tables { xsdt.append(table); } xsdt.update_checksum(); let xsdt_offset = prev_tbl_off.checked_add(prev_tbl_len as u64).unwrap(); guest_mem .write_slice(xsdt.as_slice(), xsdt_offset) .expect("Error writing XSDT table"); // RSDP let rsdp = RSDP::new(*b"CLOUDH", xsdt_offset.0); guest_mem .write_slice(rsdp.as_slice(), rsdp_offset) .expect("Error writing RSDP"); rsdp_offset }