mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
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0066ddefe1
In preparation for reorganizing how the serial output is constructed add methods to the serial devices for setting the out buffer after the device is created. Also add a method to enable flushing the output buffer to be used to write the buffer to the PTY fd once the PTY is writable. Signed-off-by: William Douglas <william.douglas@intel.com>
494 lines
14 KiB
Rust
494 lines
14 KiB
Rust
// Copyright 2021 Arm Limited (or its affiliates). All rights reserved.
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// SPDX-License-Identifier: Apache-2.0
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//! ARM PrimeCell UART(PL011)
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//!
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//! This module implements an ARM PrimeCell UART(PL011).
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//!
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use crate::{read_le_u32, write_le_u32};
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use std::collections::VecDeque;
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use std::fmt;
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use std::sync::{Arc, Barrier};
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use std::{io, result};
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use versionize::{VersionMap, Versionize, VersionizeResult};
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use versionize_derive::Versionize;
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use vm_device::interrupt::InterruptSourceGroup;
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use vm_device::BusDevice;
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use vm_migration::{
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Migratable, MigratableError, Pausable, Snapshot, Snapshottable, Transportable, VersionMapped,
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};
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/* Registers */
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const UARTDR: u64 = 0;
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const UARTRSR_UARTECR: u64 = 1;
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const UARTFR: u64 = 6;
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const UARTILPR: u64 = 8;
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const UARTIBRD: u64 = 9;
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const UARTFBRD: u64 = 10;
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const UARTLCR_H: u64 = 11;
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const UARTCR: u64 = 12;
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const UARTIFLS: u64 = 13;
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const UARTIMSC: u64 = 14;
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const UARTRIS: u64 = 15;
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const UARTMIS: u64 = 16;
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const UARTICR: u64 = 17;
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const UARTDMACR: u64 = 18;
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const PL011_INT_TX: u32 = 0x20;
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const PL011_INT_RX: u32 = 0x10;
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const PL011_FLAG_RXFF: u32 = 0x40;
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const PL011_FLAG_RXFE: u32 = 0x10;
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const PL011_ID: [u8; 8] = [0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1];
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// We are only interested in the margins.
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const AMBA_ID_LOW: u64 = 0x3f8;
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const AMBA_ID_HIGH: u64 = 0x401;
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#[derive(Debug)]
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pub enum Error {
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BadWriteOffset(u64),
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DmaNotImplemented,
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InterruptFailure(io::Error),
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WriteAllFailure(io::Error),
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FlushFailure(io::Error),
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}
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impl fmt::Display for Error {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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match self {
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Error::BadWriteOffset(offset) => write!(f, "pl011_write: Bad Write Offset: {}", offset),
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Error::DmaNotImplemented => write!(f, "pl011: DMA not implemented."),
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Error::InterruptFailure(e) => write!(f, "Failed to trigger interrupt: {}", e),
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Error::WriteAllFailure(e) => write!(f, "Failed to write: {}", e),
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Error::FlushFailure(e) => write!(f, "Failed to flush: {}", e),
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}
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}
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}
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type Result<T> = result::Result<T, Error>;
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/// A PL011 device following the PL011 specification.
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pub struct Pl011 {
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id: String,
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flags: u32,
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lcr: u32,
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rsr: u32,
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cr: u32,
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dmacr: u32,
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int_enabled: u32,
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int_level: u32,
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read_fifo: VecDeque<u8>,
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ilpr: u32,
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ibrd: u32,
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fbrd: u32,
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ifl: u32,
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read_count: u32,
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read_trigger: u32,
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irq: Arc<dyn InterruptSourceGroup>,
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out: Option<Box<dyn io::Write + Send>>,
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}
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#[derive(Versionize)]
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pub struct Pl011State {
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flags: u32,
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lcr: u32,
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rsr: u32,
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cr: u32,
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dmacr: u32,
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int_enabled: u32,
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int_level: u32,
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read_fifo: Vec<u8>,
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ilpr: u32,
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ibrd: u32,
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fbrd: u32,
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ifl: u32,
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read_count: u32,
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read_trigger: u32,
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}
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impl VersionMapped for Pl011State {}
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impl Pl011 {
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/// Constructs an AMBA PL011 UART device.
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pub fn new(
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id: String,
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irq: Arc<dyn InterruptSourceGroup>,
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out: Option<Box<dyn io::Write + Send>>,
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) -> Self {
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Self {
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id,
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flags: 0x90u32,
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lcr: 0u32,
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rsr: 0u32,
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cr: 0x300u32,
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dmacr: 0u32,
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int_enabled: 0u32,
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int_level: 0u32,
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read_fifo: VecDeque::new(),
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ilpr: 0u32,
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ibrd: 0u32,
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fbrd: 0u32,
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ifl: 0x12u32,
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read_count: 0u32,
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read_trigger: 1u32,
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irq,
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out,
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}
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}
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pub fn set_out(&mut self, out: Box<dyn io::Write + Send>) {
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self.out = Some(out);
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}
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fn state(&self) -> Pl011State {
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Pl011State {
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flags: self.flags,
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lcr: self.lcr,
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rsr: self.rsr,
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cr: self.cr,
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dmacr: self.dmacr,
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int_enabled: self.int_enabled,
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int_level: self.int_level,
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read_fifo: self.read_fifo.clone().into(),
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ilpr: self.ilpr,
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ibrd: self.ibrd,
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fbrd: self.fbrd,
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ifl: self.ifl,
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read_count: self.read_count,
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read_trigger: self.read_trigger,
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}
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}
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fn set_state(&mut self, state: &Pl011State) {
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self.flags = state.flags;
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self.lcr = state.lcr;
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self.rsr = state.rsr;
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self.cr = state.cr;
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self.dmacr = state.dmacr;
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self.int_enabled = state.int_enabled;
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self.int_level = state.int_level;
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self.read_fifo = state.read_fifo.clone().into();
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self.ilpr = state.ilpr;
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self.ibrd = state.ibrd;
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self.fbrd = state.fbrd;
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self.ifl = state.ifl;
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self.read_count = state.read_count;
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self.read_trigger = state.read_trigger;
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}
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/// Queues raw bytes for the guest to read and signals the interrupt
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pub fn queue_input_bytes(&mut self, c: &[u8]) -> vmm_sys_util::errno::Result<()> {
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self.read_fifo.extend(c);
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self.read_count += c.len() as u32;
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self.flags &= !PL011_FLAG_RXFE;
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if ((self.lcr & 0x10) == 0) || (self.read_count == 16) {
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self.flags |= PL011_FLAG_RXFF;
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}
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if self.read_count >= self.read_trigger {
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self.int_level |= PL011_INT_RX;
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self.trigger_interrupt()?;
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}
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Ok(())
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}
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pub fn flush_output(&mut self) -> result::Result<(), io::Error> {
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if let Some(out) = self.out.as_mut() {
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out.flush()?;
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}
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Ok(())
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}
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fn pl011_get_baudrate(&self) -> u32 {
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if self.fbrd == 0 {
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return 0;
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}
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let clk = 24_000_000; // We set the APB_PLCK to 24M in device tree
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(clk / ((self.ibrd << 6) + self.fbrd)) << 2
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}
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fn pl011_trace_baudrate_change(&self) {
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debug!(
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"=== New baudrate: {:#?} (clk: {:#?}Hz, ibrd: {:#?}, fbrd: {:#?}) ===",
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self.pl011_get_baudrate(),
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24_000_000, // We set the APB_PLCK to 24M in device tree
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self.ibrd,
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self.fbrd
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);
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}
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fn pl011_set_read_trigger(&mut self) {
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self.read_trigger = 1;
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}
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fn handle_write(&mut self, offset: u64, val: u32) -> Result<()> {
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match offset >> 2 {
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UARTDR => {
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self.int_level |= PL011_INT_TX;
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if let Some(out) = self.out.as_mut() {
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out.write_all(&[val.to_le_bytes()[0]])
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.map_err(Error::WriteAllFailure)?;
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out.flush().map_err(Error::FlushFailure)?;
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}
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}
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UARTRSR_UARTECR => {
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self.rsr = 0;
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}
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UARTFR => { /* Writes to Flag register are ignored.*/ }
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UARTILPR => {
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self.ilpr = val;
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}
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UARTIBRD => {
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self.ibrd = val;
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self.pl011_trace_baudrate_change();
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}
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UARTFBRD => {
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self.fbrd = val;
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self.pl011_trace_baudrate_change();
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}
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UARTLCR_H => {
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/* Reset the FIFO state on FIFO enable or disable */
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if ((self.lcr ^ val) & 0x10) != 0 {
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self.read_count = 0;
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}
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self.lcr = val;
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self.pl011_set_read_trigger();
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}
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UARTCR => {
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self.cr = val;
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}
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UARTIFLS => {
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self.ifl = val;
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self.pl011_set_read_trigger();
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}
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UARTIMSC => {
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self.int_enabled = val;
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self.trigger_interrupt().map_err(Error::InterruptFailure)?;
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}
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UARTICR => {
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self.int_level &= !val;
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self.trigger_interrupt().map_err(Error::InterruptFailure)?;
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}
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UARTDMACR => {
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self.dmacr = val;
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if (val & 3) != 0 {
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return Err(Error::DmaNotImplemented);
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}
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}
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off => {
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return Err(Error::BadWriteOffset(off));
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}
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}
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Ok(())
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}
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fn trigger_interrupt(&mut self) -> result::Result<(), io::Error> {
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self.irq.trigger(0)
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}
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}
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impl BusDevice for Pl011 {
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fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
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let v;
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let mut read_ok = true;
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if (AMBA_ID_LOW..AMBA_ID_HIGH).contains(&(offset >> 2)) {
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let index = ((offset - 0xfe0) >> 2) as usize;
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v = u32::from(PL011_ID[index]);
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} else {
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v = match offset >> 2 {
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UARTDR => {
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let c: u32;
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let r: u32;
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self.flags &= !PL011_FLAG_RXFF;
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c = self.read_fifo.pop_front().unwrap_or_default().into();
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if self.read_count > 0 {
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self.read_count -= 1;
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}
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if self.read_count == 0 {
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self.flags |= PL011_FLAG_RXFE;
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}
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if self.read_count == (self.read_trigger - 1) {
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self.int_level &= !PL011_INT_RX;
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}
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self.rsr = c >> 8;
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r = c;
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r
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}
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UARTRSR_UARTECR => self.rsr,
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UARTFR => self.flags,
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UARTILPR => self.ilpr,
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UARTIBRD => self.ibrd,
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UARTFBRD => self.fbrd,
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UARTLCR_H => self.lcr,
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UARTCR => self.cr,
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UARTIFLS => self.ifl,
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UARTIMSC => self.int_enabled,
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UARTRIS => self.int_level,
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UARTMIS => (self.int_level & self.int_enabled),
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UARTDMACR => self.dmacr,
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_ => {
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read_ok = false;
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0
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}
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}
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}
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if read_ok && data.len() <= 4 {
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write_le_u32(data, v);
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} else {
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warn!(
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"Invalid PL011 read: offset {}, data length {}",
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offset,
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data.len()
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);
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}
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}
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fn write(&mut self, _base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
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if data.len() <= 4 {
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let v = read_le_u32(data);
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if let Err(e) = self.handle_write(offset, v) {
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warn!("Failed to write to PL011 device: {}", e);
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}
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} else {
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warn!(
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"Invalid PL011 write: offset {}, data length {}",
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offset,
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data.len()
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);
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}
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None
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}
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}
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impl Snapshottable for Pl011 {
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fn id(&self) -> String {
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self.id.clone()
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}
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fn snapshot(&mut self) -> std::result::Result<Snapshot, MigratableError> {
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Snapshot::new_from_versioned_state(&self.id, &self.state())
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}
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fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
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self.set_state(&snapshot.to_versioned_state(&self.id)?);
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Ok(())
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}
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}
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impl Pausable for Pl011 {}
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impl Transportable for Pl011 {}
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impl Migratable for Pl011 {}
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#[cfg(test)]
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mod tests {
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use super::*;
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use std::io;
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use std::sync::{Arc, Mutex};
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use vm_device::interrupt::{InterruptIndex, InterruptSourceConfig};
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use vmm_sys_util::eventfd::EventFd;
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const SERIAL_NAME: &str = "serial";
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struct TestInterrupt {
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event_fd: EventFd,
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}
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impl InterruptSourceGroup for TestInterrupt {
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fn trigger(&self, _index: InterruptIndex) -> result::Result<(), std::io::Error> {
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self.event_fd.write(1)
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}
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fn update(
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&self,
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_index: InterruptIndex,
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_config: InterruptSourceConfig,
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) -> result::Result<(), std::io::Error> {
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Ok(())
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}
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fn notifier(&self, _index: InterruptIndex) -> Option<EventFd> {
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Some(self.event_fd.try_clone().unwrap())
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}
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}
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impl TestInterrupt {
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fn new(event_fd: EventFd) -> Self {
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TestInterrupt { event_fd }
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}
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}
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#[derive(Clone)]
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struct SharedBuffer {
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buf: Arc<Mutex<Vec<u8>>>,
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}
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impl SharedBuffer {
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fn new() -> SharedBuffer {
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SharedBuffer {
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buf: Arc::new(Mutex::new(Vec::new())),
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}
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}
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}
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impl io::Write for SharedBuffer {
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fn write(&mut self, buf: &[u8]) -> io::Result<usize> {
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self.buf.lock().unwrap().write(buf)
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}
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fn flush(&mut self) -> io::Result<()> {
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self.buf.lock().unwrap().flush()
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}
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}
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#[test]
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fn pl011_output() {
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let intr_evt = EventFd::new(0).unwrap();
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let pl011_out = SharedBuffer::new();
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let mut pl011 = Pl011::new(
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String::from(SERIAL_NAME),
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Arc::new(TestInterrupt::new(intr_evt.try_clone().unwrap())),
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Some(Box::new(pl011_out.clone())),
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);
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pl011.write(0, UARTDR as u64, &[b'x', b'y']);
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pl011.write(0, UARTDR as u64, &[b'a']);
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pl011.write(0, UARTDR as u64, &[b'b']);
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pl011.write(0, UARTDR as u64, &[b'c']);
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assert_eq!(
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pl011_out.buf.lock().unwrap().as_slice(),
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&[b'x', b'a', b'b', b'c']
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);
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}
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#[test]
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fn pl011_input() {
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let intr_evt = EventFd::new(0).unwrap();
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let pl011_out = SharedBuffer::new();
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let mut pl011 = Pl011::new(
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String::from(SERIAL_NAME),
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Arc::new(TestInterrupt::new(intr_evt.try_clone().unwrap())),
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Some(Box::new(pl011_out)),
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);
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// write 1 to the interrupt event fd, so that read doesn't block in case the event fd
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// counter doesn't change (for 0 it blocks)
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assert!(intr_evt.write(1).is_ok());
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pl011.queue_input_bytes(&[b'a', b'b', b'c']).unwrap();
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assert_eq!(intr_evt.read().unwrap(), 2);
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let mut data = [0u8];
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pl011.read(0, UARTDR as u64, &mut data);
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assert_eq!(data[0], b'a');
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pl011.read(0, UARTDR as u64, &mut data);
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assert_eq!(data[0], b'b');
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pl011.read(0, UARTDR as u64, &mut data);
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assert_eq!(data[0], b'c');
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}
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}
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