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When the destination mode is physical, the destination field should only be defined through bits 56-59, as defined in the IOAPIC spec. But from the APIC specification, the APIC ID is always defined on 8 bits no matter which destination mode is selected. That's why we always retrieve the destination field based on bits 56-63. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
60 lines
1.7 KiB
Rust
60 lines
1.7 KiB
Rust
// Copyright 2020, ARM Limited.
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//
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// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
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use std::io;
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use std::result;
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#[derive(Debug)]
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pub enum Error {
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/// Invalid trigger mode.
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InvalidTriggerMode,
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/// Invalid delivery mode.
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InvalidDeliveryMode,
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/// Failed creating the interrupt source group.
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CreateInterruptSourceGroup(io::Error),
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/// Failed triggering the interrupt.
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TriggerInterrupt(io::Error),
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/// Failed masking the interrupt.
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MaskInterrupt(io::Error),
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/// Failed unmasking the interrupt.
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UnmaskInterrupt(io::Error),
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/// Failed updating the interrupt.
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UpdateInterrupt(io::Error),
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/// Failed enabling the interrupt.
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EnableInterrupt(io::Error),
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}
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type Result<T> = result::Result<T, Error>;
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pub struct MsiMessage {
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// Message Address Register
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// 31-20: Base address. Fixed value (0x0FEE)
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// 19-12: Destination ID
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// 11-4: Reserved
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// 3: Redirection Hint indication
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// 2: Destination Mode
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// 1-0: Reserved
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pub addr: u32,
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// Message Data Register
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// 32-16: Reserved
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// 15: Trigger Mode. 0 = Edge, 1 = Level
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// 14: Level. 0 = Deassert, 1 = Assert
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// 13-11: Reserved
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// 10-8: Delivery Mode
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// 7-0: Vector
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pub data: u32,
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}
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// Introduce trait InterruptController to uniform the interrupt
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// service provided for devices.
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// Device manager uses this trait without caring whether it is a
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// IOAPIC (X86) or GIC (Arm).
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pub trait InterruptController: Send {
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fn service_irq(&mut self, irq: usize) -> Result<()>;
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#[cfg(target_arch = "aarch64")]
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fn enable(&self) -> Result<()>;
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#[cfg(target_arch = "x86_64")]
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fn end_of_interrupt(&mut self, vec: u8);
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}
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