mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
synced 2024-08-21 23:41:15 +00:00
The same way we mask the writes coming from the guest to the message control register related to MSI-X capability, let's do the same for MSI. The point is to prevent the guest from writing to read-only bits. The correct writable bits for MSI are only bits 0, 4, 5 and 6 of 2nd 16-bit word. Those are: * MSI Enable: 0 * Multiple Message Enable: 6-4 See "Table 7-39 Message Control Register for MSI" from "NCB-PCI_Express_Base_5.0r1.0-2019-05-22.pdf". Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com> |
||
---|---|---|
.. | ||
bus.rs | ||
configuration.rs | ||
device.rs | ||
lib.rs | ||
msi.rs | ||
msix.rs | ||
vfio_user.rs | ||
vfio.rs |