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The structure provided to the add_capability() function should only contain what comes after the capability ID and the next capability pointer, which are located on the first WORD. Because the structure TestCap included _vndr and _next fields, they were directly set after the first WORD, while the assertion was expecting to find the values of len and foo fields. Fixes #105 Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
808 lines
26 KiB
Rust
Executable File
808 lines
26 KiB
Rust
Executable File
// Copyright 2018 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE-BSD-3-Clause file.
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use std::sync::{Arc, Mutex};
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use crate::{MsixConfig, PciInterruptPin};
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use byteorder::{ByteOrder, LittleEndian};
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use std::fmt::{self, Display};
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// The number of 32bit registers in the config space, 256 bytes.
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const NUM_CONFIGURATION_REGISTERS: usize = 64;
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const STATUS_REG: usize = 1;
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const STATUS_REG_CAPABILITIES_USED_MASK: u32 = 0x0010_0000;
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const BAR0_REG: usize = 4;
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const ROM_BAR_REG: usize = 12;
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const BAR_IO_ADDR_MASK: u32 = 0xffff_fffc;
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const BAR_MEM_ADDR_MASK: u32 = 0xffff_fff0;
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const ROM_BAR_ADDR_MASK: u32 = 0xffff_f800;
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const NUM_BAR_REGS: usize = 6;
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const CAPABILITY_LIST_HEAD_OFFSET: usize = 0x34;
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const FIRST_CAPABILITY_OFFSET: usize = 0x40;
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const CAPABILITY_MAX_OFFSET: usize = 192;
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const INTERRUPT_LINE_PIN_REG: usize = 15;
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/// Represents the types of PCI headers allowed in the configuration registers.
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#[derive(Copy, Clone)]
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pub enum PciHeaderType {
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Device,
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Bridge,
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}
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/// Classes of PCI nodes.
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#[allow(dead_code)]
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#[derive(Copy, Clone)]
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pub enum PciClassCode {
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TooOld,
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MassStorage,
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NetworkController,
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DisplayController,
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MultimediaController,
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MemoryController,
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BridgeDevice,
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SimpleCommunicationController,
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BaseSystemPeripheral,
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InputDevice,
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DockingStation,
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Processor,
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SerialBusController,
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WirelessController,
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IntelligentIoController,
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EncryptionController,
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DataAcquisitionSignalProcessing,
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Other = 0xff,
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}
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impl PciClassCode {
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pub fn get_register_value(self) -> u8 {
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self as u8
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}
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}
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/// A PCI sublcass. Each class in `PciClassCode` can specify a unique set of subclasses. This trait
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/// is implemented by each subclass. It allows use of a trait object to generate configurations.
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pub trait PciSubclass {
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/// Convert this subclass to the value used in the PCI specification.
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fn get_register_value(&self) -> u8;
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}
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/// Subclasses of the MultimediaController class.
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#[allow(dead_code)]
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#[derive(Copy, Clone)]
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pub enum PciMultimediaSubclass {
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VideoController = 0x00,
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AudioController = 0x01,
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TelephonyDevice = 0x02,
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AudioDevice = 0x03,
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Other = 0x80,
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}
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impl PciSubclass for PciMultimediaSubclass {
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fn get_register_value(&self) -> u8 {
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*self as u8
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}
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}
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/// Subclasses of the BridgeDevice
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#[allow(dead_code)]
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#[derive(Copy, Clone)]
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pub enum PciBridgeSubclass {
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HostBridge = 0x00,
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IsaBridge = 0x01,
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EisaBridge = 0x02,
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McaBridge = 0x03,
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PciToPciBridge = 0x04,
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PcmciaBridge = 0x05,
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NuBusBridge = 0x06,
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CardBusBridge = 0x07,
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RACEwayBridge = 0x08,
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PciToPciSemiTransparentBridge = 0x09,
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InfiniBrandToPciHostBridge = 0x0a,
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OtherBridgeDevice = 0x80,
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}
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impl PciSubclass for PciBridgeSubclass {
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fn get_register_value(&self) -> u8 {
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*self as u8
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}
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}
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/// Subclass of the SerialBus
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#[allow(dead_code)]
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#[derive(Copy, Clone)]
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pub enum PciSerialBusSubClass {
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Firewire = 0x00,
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ACCESSbus = 0x01,
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SSA = 0x02,
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USB = 0x03,
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}
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impl PciSubclass for PciSerialBusSubClass {
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fn get_register_value(&self) -> u8 {
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*self as u8
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}
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}
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/// Mass Storage Sub Classes
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#[allow(dead_code)]
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#[derive(Copy, Clone)]
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pub enum PciMassStorageSubclass {
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SCSIStorage = 0x00,
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IDEInterface = 0x01,
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FloppyController = 0x02,
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IPIController = 0x03,
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RAIDController = 0x04,
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ATAController = 0x05,
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SATAController = 0x06,
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SerialSCSIController = 0x07,
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NVMController = 0x08,
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MassStorage = 0x80,
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}
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impl PciSubclass for PciMassStorageSubclass {
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fn get_register_value(&self) -> u8 {
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*self as u8
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}
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}
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/// Network Controller Sub Classes
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#[allow(dead_code)]
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#[derive(Copy, Clone)]
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pub enum PciNetworkControllerSubclass {
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EthernetController = 0x00,
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TokenRingController = 0x01,
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FDDIController = 0x02,
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ATMController = 0x03,
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ISDNController = 0x04,
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WorldFipController = 0x05,
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PICMGController = 0x06,
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InfinibandController = 0x07,
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FabricController = 0x08,
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NetworkController = 0x80,
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}
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impl PciSubclass for PciNetworkControllerSubclass {
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fn get_register_value(&self) -> u8 {
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*self as u8
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}
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}
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/// A PCI class programming interface. Each combination of `PciClassCode` and
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/// `PciSubclass` can specify a set of register-level programming interfaces.
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/// This trait is implemented by each programming interface.
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/// It allows use of a trait object to generate configurations.
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pub trait PciProgrammingInterface {
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/// Convert this programming interface to the value used in the PCI specification.
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fn get_register_value(&self) -> u8;
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}
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/// Types of PCI capabilities.
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#[derive(PartialEq, Copy, Clone)]
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#[allow(dead_code)]
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#[allow(non_camel_case_types)]
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#[repr(C)]
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pub enum PciCapabilityID {
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ListID = 0,
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PowerManagement = 0x01,
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AcceleratedGraphicsPort = 0x02,
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VitalProductData = 0x03,
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SlotIdentification = 0x04,
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MessageSignalledInterrupts = 0x05,
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CompactPCIHotSwap = 0x06,
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PCIX = 0x07,
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HyperTransport = 0x08,
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VendorSpecific = 0x09,
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Debugport = 0x0A,
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CompactPCICentralResourceControl = 0x0B,
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PCIStandardHotPlugController = 0x0C,
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BridgeSubsystemVendorDeviceID = 0x0D,
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AGPTargetPCIPCIbridge = 0x0E,
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SecureDevice = 0x0F,
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PCIExpress = 0x10,
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MSIX = 0x11,
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SATADataIndexConf = 0x12,
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PCIAdvancedFeatures = 0x13,
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PCIEnhancedAllocation = 0x14,
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}
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impl From<u8> for PciCapabilityID {
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fn from(c: u8) -> Self {
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match c {
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0 => PciCapabilityID::ListID,
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0x01 => PciCapabilityID::PowerManagement,
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0x02 => PciCapabilityID::AcceleratedGraphicsPort,
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0x03 => PciCapabilityID::VitalProductData,
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0x04 => PciCapabilityID::SlotIdentification,
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0x05 => PciCapabilityID::MessageSignalledInterrupts,
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0x06 => PciCapabilityID::CompactPCIHotSwap,
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0x07 => PciCapabilityID::PCIX,
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0x08 => PciCapabilityID::HyperTransport,
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0x09 => PciCapabilityID::VendorSpecific,
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0x0A => PciCapabilityID::Debugport,
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0x0B => PciCapabilityID::CompactPCICentralResourceControl,
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0x0C => PciCapabilityID::PCIStandardHotPlugController,
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0x0D => PciCapabilityID::BridgeSubsystemVendorDeviceID,
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0x0E => PciCapabilityID::AGPTargetPCIPCIbridge,
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0x0F => PciCapabilityID::SecureDevice,
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0x10 => PciCapabilityID::PCIExpress,
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0x11 => PciCapabilityID::MSIX,
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0x12 => PciCapabilityID::SATADataIndexConf,
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0x13 => PciCapabilityID::PCIAdvancedFeatures,
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0x14 => PciCapabilityID::PCIEnhancedAllocation,
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_ => PciCapabilityID::ListID,
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}
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}
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}
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/// A PCI capability list. Devices can optionally specify capabilities in their configuration space.
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pub trait PciCapability {
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fn bytes(&self) -> &[u8];
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fn id(&self) -> PciCapabilityID;
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}
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/// Contains the configuration space of a PCI node.
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/// See the [specification](https://en.wikipedia.org/wiki/PCI_configuration_space).
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/// The configuration space is accessed with DWORD reads and writes from the guest.
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pub struct PciConfiguration {
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registers: [u32; NUM_CONFIGURATION_REGISTERS],
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writable_bits: [u32; NUM_CONFIGURATION_REGISTERS], // writable bits for each register.
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bar_size: [u32; NUM_BAR_REGS],
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bar_used: [bool; NUM_BAR_REGS],
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rom_bar_size: u32,
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rom_bar_used: bool,
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// Contains the byte offset and size of the last capability.
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last_capability: Option<(usize, usize)>,
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msix_cap_reg_idx: Option<usize>,
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msix_config: Option<Arc<Mutex<MsixConfig>>>,
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}
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/// See pci_regs.h in kernel
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#[derive(Copy, Clone)]
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pub enum PciBarRegionType {
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Memory32BitRegion = 0,
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IORegion = 0x01,
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Memory64BitRegion = 0x04,
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}
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#[derive(Copy, Clone)]
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pub enum PciBarPrefetchable {
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NotPrefetchable = 0,
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Prefetchable = 0x08,
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}
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#[derive(Copy, Clone)]
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pub struct PciBarConfiguration {
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addr: u64,
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size: u64,
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reg_idx: usize,
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region_type: PciBarRegionType,
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prefetchable: PciBarPrefetchable,
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}
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#[derive(Debug)]
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pub enum Error {
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BarAddressInvalid(u64, u64),
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BarInUse(usize),
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BarInUse64(usize),
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BarInvalid(usize),
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BarInvalid64(usize),
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BarSizeInvalid(u64),
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CapabilityEmpty,
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CapabilityLengthInvalid(usize),
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CapabilitySpaceFull(usize),
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RomBarAddressInvalid(u64, u64),
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RomBarInUse(usize),
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RomBarInvalid(usize),
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RomBarSizeInvalid(u64),
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}
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pub type Result<T> = std::result::Result<T, Error>;
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impl std::error::Error for Error {}
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impl Display for Error {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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use self::Error::*;
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match self {
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BarAddressInvalid(a, s) => write!(f, "address {} size {} too big", a, s),
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BarInUse(b) => write!(f, "bar {} already used", b),
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BarInUse64(b) => write!(f, "64bit bar {} already used(requires two regs)", b),
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BarInvalid(b) => write!(f, "bar {} invalid, max {}", b, NUM_BAR_REGS - 1),
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BarInvalid64(b) => write!(
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f,
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"64bitbar {} invalid, requires two regs, max {}",
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b,
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NUM_BAR_REGS - 1
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),
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BarSizeInvalid(s) => write!(f, "bar address {} not a power of two", s),
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CapabilityEmpty => write!(f, "empty capabilities are invalid"),
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CapabilityLengthInvalid(l) => write!(f, "Invalid capability length {}", l),
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CapabilitySpaceFull(s) => write!(f, "capability of size {} doesn't fit", s),
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RomBarAddressInvalid(a, s) => write!(f, "address {} size {} too big", a, s),
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RomBarInUse(b) => write!(f, "rom bar {} already used", b),
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RomBarInvalid(b) => write!(f, "rom bar {} invalid, max {}", b, NUM_BAR_REGS - 1),
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RomBarSizeInvalid(s) => write!(f, "rom bar address {} not a power of two", s),
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}
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}
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}
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impl PciConfiguration {
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#[allow(clippy::too_many_arguments)]
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pub fn new(
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vendor_id: u16,
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device_id: u16,
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class_code: PciClassCode,
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subclass: &dyn PciSubclass,
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programming_interface: Option<&dyn PciProgrammingInterface>,
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header_type: PciHeaderType,
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subsystem_vendor_id: u16,
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subsystem_id: u16,
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msix_config: Option<Arc<Mutex<MsixConfig>>>,
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) -> Self {
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let mut registers = [0u32; NUM_CONFIGURATION_REGISTERS];
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let mut writable_bits = [0u32; NUM_CONFIGURATION_REGISTERS];
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let bar_size = [0u32; NUM_BAR_REGS];
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registers[0] = u32::from(device_id) << 16 | u32::from(vendor_id);
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// TODO(dverkamp): Status should be write-1-to-clear
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writable_bits[1] = 0x0000_ffff; // Status (r/o), command (r/w)
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let pi = if let Some(pi) = programming_interface {
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pi.get_register_value()
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} else {
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0
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};
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registers[2] = u32::from(class_code.get_register_value()) << 24
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| u32::from(subclass.get_register_value()) << 16
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| u32::from(pi) << 8;
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writable_bits[3] = 0x0000_00ff; // Cacheline size (r/w)
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match header_type {
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PciHeaderType::Device => {
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registers[3] = 0x0000_0000; // Header type 0 (device)
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writable_bits[15] = 0x0000_00ff; // Interrupt line (r/w)
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}
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PciHeaderType::Bridge => {
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registers[3] = 0x0001_0000; // Header type 1 (bridge)
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writable_bits[9] = 0xfff0_fff0; // Memory base and limit
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writable_bits[15] = 0xffff_00ff; // Bridge control (r/w), interrupt line (r/w)
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}
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};
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registers[11] = u32::from(subsystem_id) << 16 | u32::from(subsystem_vendor_id);
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PciConfiguration {
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registers,
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writable_bits,
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bar_size,
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bar_used: [false; NUM_BAR_REGS],
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rom_bar_size: 0,
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rom_bar_used: false,
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last_capability: None,
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msix_cap_reg_idx: None,
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msix_config,
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}
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}
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/// Reads a 32bit register from `reg_idx` in the register map.
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pub fn read_reg(&self, reg_idx: usize) -> u32 {
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*(self.registers.get(reg_idx).unwrap_or(&0xffff_ffff))
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}
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/// Writes a 32bit register to `reg_idx` in the register map.
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pub fn write_reg(&mut self, reg_idx: usize, value: u32) {
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let mut mask = self.writable_bits[reg_idx];
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if reg_idx >= BAR0_REG
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&& reg_idx < BAR0_REG + NUM_BAR_REGS
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&& (value & BAR_MEM_ADDR_MASK) == BAR_MEM_ADDR_MASK
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{
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// Handle very specific case where the BAR is being written with
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// all 1's to retrieve the BAR size on next BAR reading.
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mask = self.bar_size[reg_idx - 4];
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} else if reg_idx == ROM_BAR_REG && (value & ROM_BAR_ADDR_MASK) == ROM_BAR_ADDR_MASK {
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mask = self.rom_bar_size;
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}
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if let Some(r) = self.registers.get_mut(reg_idx) {
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*r = (*r & !self.writable_bits[reg_idx]) | (value & mask);
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} else {
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warn!("bad PCI register write {}", reg_idx);
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}
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}
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/// Writes a 16bit word to `offset`. `offset` must be 16bit aligned.
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pub fn write_word(&mut self, offset: usize, value: u16) {
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let shift = match offset % 4 {
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0 => 0,
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2 => 16,
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_ => {
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warn!("bad PCI config write offset {}", offset);
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return;
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}
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};
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let reg_idx = offset / 4;
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if let Some(r) = self.registers.get_mut(reg_idx) {
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let writable_mask = self.writable_bits[reg_idx];
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let mask = (0xffffu32 << shift) & writable_mask;
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let shifted_value = (u32::from(value) << shift) & writable_mask;
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*r = *r & !mask | shifted_value;
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} else {
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warn!("bad PCI config write offset {}", offset);
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}
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}
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/// Writes a byte to `offset`.
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pub fn write_byte(&mut self, offset: usize, value: u8) {
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self.write_byte_internal(offset, value, true);
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}
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/// Writes a byte to `offset`, optionally enforcing read-only bits.
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fn write_byte_internal(&mut self, offset: usize, value: u8, apply_writable_mask: bool) {
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let shift = (offset % 4) * 8;
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let reg_idx = offset / 4;
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if let Some(r) = self.registers.get_mut(reg_idx) {
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let writable_mask = if apply_writable_mask {
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self.writable_bits[reg_idx]
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} else {
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0xffff_ffff
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};
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let mask = (0xffu32 << shift) & writable_mask;
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let shifted_value = (u32::from(value) << shift) & writable_mask;
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*r = *r & !mask | shifted_value;
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} else {
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warn!("bad PCI config write offset {}", offset);
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}
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}
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/// Adds a region specified by `config`. Configures the specified BAR(s) to
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/// report this region and size to the guest kernel. Enforces a few constraints
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/// (i.e, region size must be power of two, register not already used). Returns 'None' on
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/// failure all, `Some(BarIndex)` on success.
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pub fn add_pci_bar(&mut self, config: &PciBarConfiguration) -> Result<usize> {
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if self.bar_used[config.reg_idx] {
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return Err(Error::BarInUse(config.reg_idx));
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}
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if config.size.count_ones() != 1 {
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return Err(Error::BarSizeInvalid(config.size));
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}
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if config.reg_idx >= NUM_BAR_REGS {
|
|
return Err(Error::BarInvalid(config.reg_idx));
|
|
}
|
|
|
|
let bar_idx = BAR0_REG + config.reg_idx;
|
|
let end_addr = config
|
|
.addr
|
|
.checked_add(config.size - 1)
|
|
.ok_or_else(|| Error::BarAddressInvalid(config.addr, config.size))?;
|
|
match config.region_type {
|
|
PciBarRegionType::Memory32BitRegion | PciBarRegionType::IORegion => {
|
|
if end_addr > u64::from(u32::max_value()) {
|
|
return Err(Error::BarAddressInvalid(config.addr, config.size));
|
|
}
|
|
}
|
|
PciBarRegionType::Memory64BitRegion => {
|
|
if config.reg_idx + 1 >= NUM_BAR_REGS {
|
|
return Err(Error::BarInvalid64(config.reg_idx));
|
|
}
|
|
|
|
if end_addr > u64::max_value() {
|
|
return Err(Error::BarAddressInvalid(config.addr, config.size));
|
|
}
|
|
|
|
if self.bar_used[config.reg_idx + 1] {
|
|
return Err(Error::BarInUse64(config.reg_idx));
|
|
}
|
|
|
|
self.registers[bar_idx + 1] = (config.addr >> 32) as u32;
|
|
self.writable_bits[bar_idx + 1] = 0xffff_ffff;
|
|
self.bar_size[config.reg_idx + 1] = (config.size >> 32) as u32;
|
|
self.bar_used[config.reg_idx + 1] = true;
|
|
}
|
|
}
|
|
|
|
let (mask, lower_bits) = match config.region_type {
|
|
PciBarRegionType::Memory32BitRegion | PciBarRegionType::Memory64BitRegion => (
|
|
BAR_MEM_ADDR_MASK,
|
|
config.prefetchable as u32 | config.region_type as u32,
|
|
),
|
|
PciBarRegionType::IORegion => (BAR_IO_ADDR_MASK, config.region_type as u32),
|
|
};
|
|
|
|
self.registers[bar_idx] = ((config.addr as u32) & mask) | lower_bits;
|
|
self.writable_bits[bar_idx] = mask;
|
|
self.bar_size[config.reg_idx] = config.size as u32;
|
|
self.bar_used[config.reg_idx] = true;
|
|
Ok(config.reg_idx)
|
|
}
|
|
|
|
/// Adds rom expansion BAR.
|
|
pub fn add_pci_rom_bar(&mut self, config: &PciBarConfiguration, active: u32) -> Result<usize> {
|
|
if self.rom_bar_used {
|
|
return Err(Error::RomBarInUse(config.reg_idx));
|
|
}
|
|
|
|
if config.size.count_ones() != 1 {
|
|
return Err(Error::RomBarSizeInvalid(config.size));
|
|
}
|
|
|
|
if config.reg_idx != ROM_BAR_REG {
|
|
return Err(Error::RomBarInvalid(config.reg_idx));
|
|
}
|
|
|
|
let end_addr = config
|
|
.addr
|
|
.checked_add(config.size - 1)
|
|
.ok_or_else(|| Error::RomBarAddressInvalid(config.addr, config.size))?;
|
|
|
|
if end_addr > u64::from(u32::max_value()) {
|
|
return Err(Error::RomBarAddressInvalid(config.addr, config.size));
|
|
}
|
|
|
|
self.registers[config.reg_idx] = (config.addr as u32) | active;
|
|
self.writable_bits[config.reg_idx] = ROM_BAR_ADDR_MASK;
|
|
self.rom_bar_size = config.size as u32;
|
|
self.rom_bar_used = true;
|
|
Ok(config.reg_idx)
|
|
}
|
|
|
|
/// Returns the address of the given 32 bits BAR region.
|
|
pub fn get_bar32_addr(&self, bar_num: usize) -> u32 {
|
|
let bar_idx = BAR0_REG + bar_num;
|
|
|
|
self.registers[bar_idx] & BAR_MEM_ADDR_MASK
|
|
}
|
|
|
|
/// Returns the address of the given 64 bits BAR region.
|
|
pub fn get_bar64_addr(&self, bar_num: usize) -> u64 {
|
|
let bar_idx = BAR0_REG + bar_num;
|
|
|
|
u64::from(self.registers[bar_idx] & BAR_MEM_ADDR_MASK)
|
|
| (u64::from(self.registers[bar_idx + 1]) << 32)
|
|
}
|
|
|
|
/// Configures the IRQ line and pin used by this device.
|
|
pub fn set_irq(&mut self, line: u8, pin: PciInterruptPin) {
|
|
// `pin` is 1-based in the pci config space.
|
|
let pin_idx = (pin as u32) + 1;
|
|
self.registers[INTERRUPT_LINE_PIN_REG] = (self.registers[INTERRUPT_LINE_PIN_REG]
|
|
& 0xffff_0000)
|
|
| (pin_idx << 8)
|
|
| u32::from(line);
|
|
}
|
|
|
|
/// Adds the capability `cap_data` to the list of capabilities.
|
|
/// `cap_data` should include the two-byte PCI capability header (type, next),
|
|
/// but not populate it. Correct values will be generated automatically based
|
|
/// on `cap_data.id()`.
|
|
pub fn add_capability(&mut self, cap_data: &dyn PciCapability) -> Result<usize> {
|
|
let total_len = cap_data.bytes().len();
|
|
// Check that the length is valid.
|
|
if cap_data.bytes().is_empty() {
|
|
return Err(Error::CapabilityEmpty);
|
|
}
|
|
let (cap_offset, tail_offset) = match self.last_capability {
|
|
Some((offset, len)) => (Self::next_dword(offset, len), offset + 1),
|
|
None => (FIRST_CAPABILITY_OFFSET, CAPABILITY_LIST_HEAD_OFFSET),
|
|
};
|
|
let end_offset = cap_offset
|
|
.checked_add(total_len)
|
|
.ok_or_else(|| Error::CapabilitySpaceFull(total_len))?;
|
|
if end_offset > CAPABILITY_MAX_OFFSET {
|
|
return Err(Error::CapabilitySpaceFull(total_len));
|
|
}
|
|
self.registers[STATUS_REG] |= STATUS_REG_CAPABILITIES_USED_MASK;
|
|
self.write_byte_internal(tail_offset, cap_offset as u8, false);
|
|
self.write_byte_internal(cap_offset, cap_data.id() as u8, false);
|
|
self.write_byte_internal(cap_offset + 1, 0, false); // Next pointer.
|
|
for (i, byte) in cap_data.bytes().iter().enumerate() {
|
|
self.write_byte_internal(cap_offset + i + 2, *byte, false);
|
|
}
|
|
self.last_capability = Some((cap_offset, total_len));
|
|
|
|
if cap_data.id() == PciCapabilityID::MSIX {
|
|
self.msix_cap_reg_idx = Some(cap_offset / 4);
|
|
}
|
|
|
|
Ok(cap_offset)
|
|
}
|
|
|
|
// Find the next aligned offset after the one given.
|
|
fn next_dword(offset: usize, len: usize) -> usize {
|
|
let next = offset + len;
|
|
(next + 3) & !3
|
|
}
|
|
|
|
pub fn write_config_register(&mut self, reg_idx: usize, offset: u64, data: &[u8]) {
|
|
if offset as usize + data.len() > 4 {
|
|
return;
|
|
}
|
|
|
|
// Handle potential write to MSI-X message control register
|
|
if let Some(msix_cap_reg_idx) = self.msix_cap_reg_idx {
|
|
if let Some(msix_config) = &self.msix_config {
|
|
if msix_cap_reg_idx == reg_idx && offset == 2 && data.len() == 2 {
|
|
msix_config
|
|
.lock()
|
|
.unwrap()
|
|
.set_msg_ctl(LittleEndian::read_u16(data));
|
|
}
|
|
}
|
|
}
|
|
|
|
match data.len() {
|
|
1 => self.write_byte(reg_idx * 4 + offset as usize, data[0]),
|
|
2 => self.write_word(
|
|
reg_idx * 4 + offset as usize,
|
|
u16::from(data[0]) | u16::from(data[1]) << 8,
|
|
),
|
|
4 => self.write_reg(reg_idx, LittleEndian::read_u32(data)),
|
|
_ => (),
|
|
}
|
|
}
|
|
|
|
pub fn read_config_register(&self, reg_idx: usize) -> u32 {
|
|
self.read_reg(reg_idx)
|
|
}
|
|
}
|
|
|
|
impl Default for PciBarConfiguration {
|
|
fn default() -> Self {
|
|
PciBarConfiguration {
|
|
reg_idx: 0,
|
|
addr: 0,
|
|
size: 0,
|
|
region_type: PciBarRegionType::Memory64BitRegion,
|
|
prefetchable: PciBarPrefetchable::NotPrefetchable,
|
|
}
|
|
}
|
|
}
|
|
|
|
impl PciBarConfiguration {
|
|
pub fn new(
|
|
reg_idx: usize,
|
|
size: u64,
|
|
region_type: PciBarRegionType,
|
|
prefetchable: PciBarPrefetchable,
|
|
) -> Self {
|
|
PciBarConfiguration {
|
|
reg_idx,
|
|
addr: 0,
|
|
size,
|
|
region_type,
|
|
prefetchable,
|
|
}
|
|
}
|
|
|
|
pub fn set_register_index(mut self, reg_idx: usize) -> Self {
|
|
self.reg_idx = reg_idx;
|
|
self
|
|
}
|
|
|
|
pub fn set_address(mut self, addr: u64) -> Self {
|
|
self.addr = addr;
|
|
self
|
|
}
|
|
|
|
pub fn set_size(mut self, size: u64) -> Self {
|
|
self.size = size;
|
|
self
|
|
}
|
|
|
|
pub fn get_size(&self) -> u64 {
|
|
self.size
|
|
}
|
|
|
|
pub fn set_region_type(mut self, region_type: PciBarRegionType) -> Self {
|
|
self.region_type = region_type;
|
|
self
|
|
}
|
|
}
|
|
|
|
#[cfg(test)]
|
|
mod tests {
|
|
use vm_memory::ByteValued;
|
|
|
|
use super::*;
|
|
|
|
#[repr(packed)]
|
|
#[derive(Clone, Copy, Default)]
|
|
#[allow(dead_code)]
|
|
struct TestCap {
|
|
len: u8,
|
|
foo: u8,
|
|
}
|
|
|
|
// It is safe to implement BytesValued; all members are simple numbers and any value is valid.
|
|
unsafe impl ByteValued for TestCap {}
|
|
|
|
impl PciCapability for TestCap {
|
|
fn bytes(&self) -> &[u8] {
|
|
self.as_slice()
|
|
}
|
|
|
|
fn id(&self) -> PciCapabilityID {
|
|
PciCapabilityID::VendorSpecific
|
|
}
|
|
}
|
|
|
|
#[test]
|
|
fn add_capability() {
|
|
let mut cfg = PciConfiguration::new(
|
|
0x1234,
|
|
0x5678,
|
|
PciClassCode::MultimediaController,
|
|
&PciMultimediaSubclass::AudioController,
|
|
None,
|
|
PciHeaderType::Device,
|
|
0xABCD,
|
|
0x2468,
|
|
None,
|
|
);
|
|
|
|
// Add two capabilities with different contents.
|
|
let cap1 = TestCap { len: 4, foo: 0xAA };
|
|
let cap1_offset = cfg.add_capability(&cap1).unwrap();
|
|
assert_eq!(cap1_offset % 4, 0);
|
|
|
|
let cap2 = TestCap {
|
|
len: 0x04,
|
|
foo: 0x55,
|
|
};
|
|
let cap2_offset = cfg.add_capability(&cap2).unwrap();
|
|
assert_eq!(cap2_offset % 4, 0);
|
|
|
|
// The capability list head should be pointing to cap1.
|
|
let cap_ptr = cfg.read_reg(CAPABILITY_LIST_HEAD_OFFSET / 4) & 0xFF;
|
|
assert_eq!(cap1_offset, cap_ptr as usize);
|
|
|
|
// Verify the contents of the capabilities.
|
|
let cap1_data = cfg.read_reg(cap1_offset / 4);
|
|
assert_eq!(cap1_data & 0xFF, 0x09); // capability ID
|
|
assert_eq!((cap1_data >> 8) & 0xFF, cap2_offset as u32); // next capability pointer
|
|
assert_eq!((cap1_data >> 16) & 0xFF, 0x04); // cap1.len
|
|
assert_eq!((cap1_data >> 24) & 0xFF, 0xAA); // cap1.foo
|
|
|
|
let cap2_data = cfg.read_reg(cap2_offset / 4);
|
|
assert_eq!(cap2_data & 0xFF, 0x09); // capability ID
|
|
assert_eq!((cap2_data >> 8) & 0xFF, 0x00); // next capability pointer
|
|
assert_eq!((cap2_data >> 16) & 0xFF, 0x04); // cap2.len
|
|
assert_eq!((cap2_data >> 24) & 0xFF, 0x55); // cap2.foo
|
|
}
|
|
|
|
#[derive(Copy, Clone)]
|
|
enum TestPI {
|
|
Test = 0x5a,
|
|
}
|
|
|
|
impl PciProgrammingInterface for TestPI {
|
|
fn get_register_value(&self) -> u8 {
|
|
*self as u8
|
|
}
|
|
}
|
|
|
|
#[test]
|
|
fn class_code() {
|
|
let cfg = PciConfiguration::new(
|
|
0x1234,
|
|
0x5678,
|
|
PciClassCode::MultimediaController,
|
|
&PciMultimediaSubclass::AudioController,
|
|
Some(&TestPI::Test),
|
|
PciHeaderType::Device,
|
|
0xABCD,
|
|
0x2468,
|
|
None,
|
|
);
|
|
|
|
let class_reg = cfg.read_reg(2);
|
|
let class_code = (class_reg >> 24) & 0xFF;
|
|
let subclass = (class_reg >> 16) & 0xFF;
|
|
let prog_if = (class_reg >> 8) & 0xFF;
|
|
assert_eq!(class_code, 0x04);
|
|
assert_eq!(subclass, 0x01);
|
|
assert_eq!(prog_if, 0x5a);
|
|
}
|
|
}
|