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Relying on helpers for creating the ACPI tables and to add each table to the HOB, this patch connects the dot to provide the set of ACPI tables to the TD firmware. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
823 lines
25 KiB
Rust
823 lines
25 KiB
Rust
// Copyright © 2019 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0
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//
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use crate::cpu::CpuManager;
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use crate::device_manager::DeviceManager;
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use crate::memory_manager::MemoryManager;
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use crate::pci_segment::PciSegment;
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use crate::{GuestMemoryMmap, GuestRegionMmap};
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use acpi_tables::sdt::GenericAddress;
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use acpi_tables::{aml::Aml, rsdp::Rsdp, sdt::Sdt};
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#[cfg(target_arch = "aarch64")]
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use arch::aarch64::DeviceInfoForFdt;
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#[cfg(target_arch = "aarch64")]
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use arch::DeviceType;
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#[cfg(any(target_arch = "aarch64", feature = "acpi"))]
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use arch::NumaNodes;
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use bitflags::bitflags;
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use pci::PciBdf;
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use std::sync::{Arc, Mutex};
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use std::time::Instant;
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use vm_memory::{Address, ByteValued, Bytes, GuestAddress, GuestMemoryRegion};
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/* Values for Type in APIC sub-headers */
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#[cfg(target_arch = "x86_64")]
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pub const ACPI_APIC_PROCESSOR: u8 = 0;
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#[cfg(target_arch = "x86_64")]
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pub const ACPI_APIC_IO: u8 = 1;
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#[cfg(target_arch = "x86_64")]
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pub const ACPI_APIC_XRUPT_OVERRIDE: u8 = 2;
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#[cfg(target_arch = "aarch64")]
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pub const ACPI_APIC_GENERIC_CPU_INTERFACE: u8 = 11;
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#[cfg(target_arch = "aarch64")]
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pub const ACPI_APIC_GENERIC_DISTRIBUTOR: u8 = 12;
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#[cfg(target_arch = "aarch64")]
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pub const ACPI_APIC_GENERIC_REDISTRIBUTOR: u8 = 14;
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#[cfg(target_arch = "aarch64")]
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pub const ACPI_APIC_GENERIC_TRANSLATOR: u8 = 15;
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#[allow(dead_code)]
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#[repr(packed)]
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#[derive(Default)]
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struct PciRangeEntry {
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pub base_address: u64,
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pub segment: u16,
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pub start: u8,
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pub end: u8,
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_reserved: u32,
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}
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#[allow(dead_code)]
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#[repr(packed)]
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#[derive(Default)]
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struct MemoryAffinity {
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pub type_: u8,
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pub length: u8,
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pub proximity_domain: u32,
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_reserved1: u16,
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pub base_addr_lo: u32,
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pub base_addr_hi: u32,
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pub length_lo: u32,
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pub length_hi: u32,
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_reserved2: u32,
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pub flags: u32,
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_reserved3: u64,
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}
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#[allow(dead_code)]
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#[repr(packed)]
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#[derive(Default)]
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struct ProcessorLocalX2ApicAffinity {
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pub type_: u8,
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pub length: u8,
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_reserved1: u16,
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pub proximity_domain: u32,
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pub x2apic_id: u32,
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pub flags: u32,
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pub clock_domain: u32,
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_reserved2: u32,
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}
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#[allow(dead_code)]
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#[repr(packed)]
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#[derive(Default)]
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struct ProcessorGiccAffinity {
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pub type_: u8,
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pub length: u8,
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pub proximity_domain: u32,
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pub acpi_processor_uid: u32,
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pub flags: u32,
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pub clock_domain: u32,
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}
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bitflags! {
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pub struct MemAffinityFlags: u32 {
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const NOFLAGS = 0;
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const ENABLE = 0b1;
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const HOTPLUGGABLE = 0b10;
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const NON_VOLATILE = 0b100;
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}
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}
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impl MemoryAffinity {
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fn from_region(
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region: &Arc<GuestRegionMmap>,
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proximity_domain: u32,
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flags: MemAffinityFlags,
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) -> Self {
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Self::from_range(
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region.start_addr().raw_value(),
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region.len(),
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proximity_domain,
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flags,
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)
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}
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fn from_range(
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base_addr: u64,
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size: u64,
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proximity_domain: u32,
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flags: MemAffinityFlags,
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) -> Self {
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let base_addr_lo = (base_addr & 0xffff_ffff) as u32;
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let base_addr_hi = (base_addr >> 32) as u32;
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let length_lo = (size & 0xffff_ffff) as u32;
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let length_hi = (size >> 32) as u32;
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MemoryAffinity {
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type_: 1,
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length: 40,
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proximity_domain,
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base_addr_lo,
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base_addr_hi,
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length_lo,
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length_hi,
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flags: flags.bits(),
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..Default::default()
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}
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}
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}
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#[allow(dead_code)]
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#[repr(packed)]
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#[derive(Default)]
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struct ViotVirtioPciNode {
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pub type_: u8,
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_reserved: u8,
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pub length: u16,
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pub pci_segment: u16,
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pub pci_bdf_number: u16,
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_reserved2: [u8; 8],
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}
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#[allow(dead_code)]
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#[repr(packed)]
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#[derive(Default)]
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struct ViotPciRangeNode {
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pub type_: u8,
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_reserved: u8,
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pub length: u16,
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pub endpoint_start: u32,
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pub pci_segment_start: u16,
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pub pci_segment_end: u16,
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pub pci_bdf_start: u16,
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pub pci_bdf_end: u16,
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pub output_node: u16,
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_reserved2: [u8; 6],
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}
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pub fn create_dsdt_table(
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device_manager: &Arc<Mutex<DeviceManager>>,
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cpu_manager: &Arc<Mutex<CpuManager>>,
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memory_manager: &Arc<Mutex<MemoryManager>>,
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) -> Sdt {
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// DSDT
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let mut dsdt = Sdt::new(*b"DSDT", 36, 6, *b"CLOUDH", *b"CHDSDT ", 1);
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let mut bytes = Vec::new();
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device_manager.lock().unwrap().append_aml_bytes(&mut bytes);
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cpu_manager.lock().unwrap().append_aml_bytes(&mut bytes);
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memory_manager.lock().unwrap().append_aml_bytes(&mut bytes);
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dsdt.append_slice(&bytes);
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dsdt
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}
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fn create_facp_table(dsdt_offset: GuestAddress) -> Sdt {
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// Revision 6 of the ACPI FADT table is 276 bytes long
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let mut facp = Sdt::new(*b"FACP", 276, 6, *b"CLOUDH", *b"CHFACP ", 1);
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// x86_64 specific fields
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#[cfg(target_arch = "x86_64")]
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{
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// PM_TMR_BLK I/O port
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facp.write(76, 0xb008u32);
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// RESET_REG
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facp.write(116, GenericAddress::io_port_address::<u8>(0x3c0));
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// RESET_VALUE
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facp.write(128, 1u8);
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// X_PM_TMR_BLK
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facp.write(208, GenericAddress::io_port_address::<u32>(0xb008));
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// SLEEP_CONTROL_REG
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facp.write(244, GenericAddress::io_port_address::<u8>(0x3c0));
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// SLEEP_STATUS_REG
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facp.write(256, GenericAddress::io_port_address::<u8>(0x3c0));
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}
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// aarch64 specific fields
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#[cfg(target_arch = "aarch64")]
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// ARM_BOOT_ARCH: enable PSCI with HVC enable-method
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facp.write(129, 3u16);
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// Architecture common fields
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// HW_REDUCED_ACPI, RESET_REG_SUP, TMR_VAL_EXT
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let fadt_flags: u32 = 1 << 20 | 1 << 10 | 1 << 8;
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facp.write(112, fadt_flags);
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// FADT minor version
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facp.write(131, 3u8);
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// X_DSDT
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facp.write(140, dsdt_offset.0);
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// Hypervisor Vendor Identity
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facp.write(268, b"CLOUDHYP");
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facp.update_checksum();
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facp
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}
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fn create_mcfg_table(pci_segments: &[PciSegment]) -> Sdt {
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let mut mcfg = Sdt::new(*b"MCFG", 36, 1, *b"CLOUDH", *b"CHMCFG ", 1);
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// MCFG reserved 8 bytes
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mcfg.append(0u64);
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for segment in pci_segments {
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// 32-bit PCI enhanced configuration mechanism
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mcfg.append(PciRangeEntry {
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base_address: segment.mmio_config_address,
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segment: segment.id,
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start: 0,
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end: 0,
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..Default::default()
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});
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}
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mcfg
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}
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fn create_srat_table(numa_nodes: &NumaNodes) -> Sdt {
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let mut srat = Sdt::new(*b"SRAT", 36, 3, *b"CLOUDH", *b"CHSRAT ", 1);
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// SRAT reserved 12 bytes
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srat.append_slice(&[0u8; 12]);
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// Check the MemoryAffinity structure is the right size as expected by
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// the ACPI specification.
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assert_eq!(std::mem::size_of::<MemoryAffinity>(), 40);
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for (node_id, node) in numa_nodes.iter() {
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let proximity_domain = *node_id as u32;
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for region in &node.memory_regions {
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srat.append(MemoryAffinity::from_region(
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region,
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proximity_domain,
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MemAffinityFlags::ENABLE,
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))
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}
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for region in &node.hotplug_regions {
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srat.append(MemoryAffinity::from_region(
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region,
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proximity_domain,
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MemAffinityFlags::ENABLE | MemAffinityFlags::HOTPLUGGABLE,
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))
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}
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#[cfg(target_arch = "x86_64")]
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for section in &node.sgx_epc_sections {
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srat.append(MemoryAffinity::from_range(
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section.start().raw_value(),
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section.size(),
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proximity_domain,
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MemAffinityFlags::ENABLE,
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))
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}
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for cpu in &node.cpus {
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let x2apic_id = *cpu as u32;
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// Flags
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// - Enabled = 1 (bit 0)
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// - Reserved bits 1-31
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let flags = 1;
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#[cfg(target_arch = "x86_64")]
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srat.append(ProcessorLocalX2ApicAffinity {
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type_: 2,
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length: 24,
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proximity_domain,
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x2apic_id,
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flags,
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clock_domain: 0,
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..Default::default()
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});
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#[cfg(target_arch = "aarch64")]
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srat.append(ProcessorGiccAffinity {
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type_: 3,
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length: 18,
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proximity_domain,
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acpi_processor_uid: x2apic_id,
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flags,
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clock_domain: 0,
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});
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}
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}
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srat
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}
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fn create_slit_table(numa_nodes: &NumaNodes) -> Sdt {
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let mut slit = Sdt::new(*b"SLIT", 36, 1, *b"CLOUDH", *b"CHSLIT ", 1);
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// Number of System Localities on 8 bytes.
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slit.append(numa_nodes.len() as u64);
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let existing_nodes: Vec<u32> = numa_nodes.keys().cloned().collect();
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for (node_id, node) in numa_nodes.iter() {
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let distances = &node.distances;
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for i in existing_nodes.iter() {
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let dist: u8 = if *node_id == *i {
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10
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} else if let Some(distance) = distances.get(i) {
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*distance as u8
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} else {
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20
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};
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slit.append(dist);
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}
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}
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slit
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}
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#[cfg(target_arch = "aarch64")]
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fn create_gtdt_table() -> Sdt {
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const ARCH_TIMER_NS_EL2_IRQ: u32 = 10;
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const ARCH_TIMER_VIRT_IRQ: u32 = 11;
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const ARCH_TIMER_S_EL1_IRQ: u32 = 13;
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const ARCH_TIMER_NS_EL1_IRQ: u32 = 14;
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const ACPI_GTDT_INTERRUPT_MODE_LEVEL: u32 = 0;
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const ACPI_GTDT_CAP_ALWAYS_ON: u32 = 1 << 2;
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let irqflags: u32 = ACPI_GTDT_INTERRUPT_MODE_LEVEL;
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// GTDT
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let mut gtdt = Sdt::new(*b"GTDT", 104, 2, *b"CLOUDH", *b"CHGTDT ", 1);
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// Secure EL1 Timer GSIV
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gtdt.write(48, (ARCH_TIMER_S_EL1_IRQ + 16) as u32);
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// Secure EL1 Timer Flags
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gtdt.write(52, irqflags);
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// Non-Secure EL1 Timer GSIV
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gtdt.write(56, (ARCH_TIMER_NS_EL1_IRQ + 16) as u32);
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// Non-Secure EL1 Timer Flags
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gtdt.write(60, (irqflags | ACPI_GTDT_CAP_ALWAYS_ON) as u32);
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// Virtual EL1 Timer GSIV
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gtdt.write(64, (ARCH_TIMER_VIRT_IRQ + 16) as u32);
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// Virtual EL1 Timer Flags
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gtdt.write(68, irqflags);
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// EL2 Timer GSIV
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gtdt.write(72, (ARCH_TIMER_NS_EL2_IRQ + 16) as u32);
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// EL2 Timer Flags
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gtdt.write(76, irqflags);
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gtdt.update_checksum();
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gtdt
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}
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#[cfg(target_arch = "aarch64")]
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fn create_spcr_table(base_address: u64, gsi: u32) -> Sdt {
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// SPCR
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let mut spcr = Sdt::new(*b"SPCR", 80, 2, *b"CLOUDH", *b"CHSPCR ", 1);
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// Interface Type
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spcr.write(36, 3u8);
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// Base Address in format ACPI Generic Address Structure
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spcr.write(40, GenericAddress::mmio_address::<u8>(base_address));
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// Interrupt Type: Bit[3] ARMH GIC interrupt
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spcr.write(52, (1 << 3) as u8);
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// Global System Interrupt used by the UART
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spcr.write(54, (gsi as u32).to_le());
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// Baud Rate: 3 = 9600
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spcr.write(58, 3u8);
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// Stop Bits: 1 Stop bit
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spcr.write(60, 1u8);
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// Flow Control: Bit[1] = RTS/CTS hardware flow control
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spcr.write(61, (1 << 1) as u8);
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// PCI Device ID: Not a PCI device
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spcr.write(64, 0xffff_u16);
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// PCI Vendor ID: Not a PCI device
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spcr.write(66, 0xffff_u16);
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spcr.update_checksum();
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spcr
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}
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#[cfg(target_arch = "aarch64")]
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fn create_dbg2_table(base_address: u64) -> Sdt {
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let namespace = "_SB_.COM1";
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let debug_device_info_offset = 44usize;
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let debug_device_info_len: u16 = 22 /* BaseAddressRegisterOffset */ +
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12 /* BaseAddressRegister */ +
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4 /* AddressSize */ +
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namespace.len() as u16 + 1 /* zero-terminated */;
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let tbl_len: u32 = debug_device_info_offset as u32 + debug_device_info_len as u32;
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let mut dbg2 = Sdt::new(*b"DBG2", tbl_len, 0, *b"CLOUDH", *b"CHDBG2 ", 1);
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/* OffsetDbgDeviceInfo */
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dbg2.write_u32(36, 44);
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/* NumberDbgDeviceInfo */
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dbg2.write_u32(40, 1);
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/* Debug Device Information structure */
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/* Offsets are calculated from the start of this structure. */
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let namespace_offset = 38u16;
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let base_address_register_offset = 22u16;
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let address_size_offset = 34u16;
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/* Revision */
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dbg2.write_u8(debug_device_info_offset, 0);
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/* Length */
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dbg2.write_u16(debug_device_info_offset + 1, debug_device_info_len);
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/* NumberofGenericAddressRegisters */
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dbg2.write_u8(debug_device_info_offset + 3, 1);
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/* NameSpaceStringLength */
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dbg2.write_u16(debug_device_info_offset + 4, namespace.len() as u16 + 1);
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/* NameSpaceStringOffset */
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dbg2.write_u16(debug_device_info_offset + 6, namespace_offset);
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/* OemDataLength */
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dbg2.write_u16(debug_device_info_offset + 8, 0);
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/* OemDataOffset */
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dbg2.write_u16(debug_device_info_offset + 10, 0);
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/* Port Type */
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dbg2.write_u16(debug_device_info_offset + 12, 0x8000);
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/* Port Subtype */
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dbg2.write_u16(debug_device_info_offset + 14, 0x0003);
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/* Reserved */
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dbg2.write_u16(debug_device_info_offset + 16, 0);
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/* BaseAddressRegisterOffset */
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dbg2.write_u16(debug_device_info_offset + 18, base_address_register_offset);
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/* AddressSizeOffset */
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dbg2.write_u16(debug_device_info_offset + 20, address_size_offset);
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/* BaseAddressRegister */
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dbg2.write(
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debug_device_info_offset + base_address_register_offset as usize,
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GenericAddress::mmio_address::<u8>(base_address),
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);
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/* AddressSize */
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dbg2.write_u32(
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debug_device_info_offset + address_size_offset as usize,
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0x1000,
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);
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/* NamespaceString, zero-terminated ASCII */
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for (k, c) in namespace.chars().enumerate() {
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dbg2.write_u8(
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debug_device_info_offset + namespace_offset as usize + k,
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c as u8,
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);
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}
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dbg2.write_u8(
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debug_device_info_offset + namespace_offset as usize + namespace.len(),
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0,
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);
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dbg2.update_checksum();
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dbg2
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}
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#[cfg(target_arch = "aarch64")]
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fn create_iort_table(pci_segments: &[PciSegment]) -> Sdt {
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const ACPI_IORT_NODE_ITS_GROUP: u8 = 0x00;
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const ACPI_IORT_NODE_PCI_ROOT_COMPLEX: u8 = 0x02;
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const ACPI_IORT_NODE_ROOT_COMPLEX_OFFSET: usize = 72;
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const ACPI_IORT_NODE_ROOT_COMPLEX_SIZE: usize = 60;
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// The IORT table containes:
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// - Header (size = 40)
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// - 1 x ITS Group Node (size = 24)
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// - N x Root Complex Node (N = number of pci segments, size = 60 x N)
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let iort_table_size: u32 = (ACPI_IORT_NODE_ROOT_COMPLEX_OFFSET
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+ ACPI_IORT_NODE_ROOT_COMPLEX_SIZE * pci_segments.len())
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as u32;
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let mut iort = Sdt::new(*b"IORT", iort_table_size, 2, *b"CLOUDH", *b"CHIORT ", 1);
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iort.write(36, ((1 + pci_segments.len()) as u32).to_le());
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iort.write(40, (48u32).to_le());
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// ITS group node
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iort.write(48, ACPI_IORT_NODE_ITS_GROUP as u8);
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// Length of the ITS group node in bytes
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iort.write(49, (24u16).to_le());
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// ITS counts
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iort.write(64, (1u32).to_le());
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// Root Complex Nodes
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for (i, segment) in pci_segments.iter().enumerate() {
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let node_offset: usize =
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ACPI_IORT_NODE_ROOT_COMPLEX_OFFSET + i * ACPI_IORT_NODE_ROOT_COMPLEX_SIZE;
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iort.write(node_offset, ACPI_IORT_NODE_PCI_ROOT_COMPLEX as u8);
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// Length of the root complex node in bytes
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iort.write(
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node_offset + 1,
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(ACPI_IORT_NODE_ROOT_COMPLEX_SIZE as u16).to_le(),
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);
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// Revision
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iort.write(node_offset + 3, (3u8).to_le());
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// Node ID
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iort.write(node_offset + 4, (segment.id as u32).to_le());
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// Mapping counts
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iort.write(node_offset + 8, (1u32).to_le());
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// Offset from the start of the RC node to the start of its Array of ID mappings
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iort.write(node_offset + 12, (36u32).to_le());
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// Fully coherent device
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iort.write(node_offset + 16, (1u32).to_le());
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// CCA = CPM = DCAS = 1
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iort.write(node_offset + 24, 3u8);
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// PCI segment number
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iort.write(node_offset + 28, (segment.id as u32).to_le());
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// Memory address size limit
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iort.write(node_offset + 32, (64u8).to_le());
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// From offset 32 onward is the space for ID mappings Array.
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// Now we have only one mapping.
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let mapping_offset: usize = node_offset + 36;
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// The lowest value in the input range
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iort.write(mapping_offset, (0u32).to_le());
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// The number of IDs in the range minus one:
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// This should cover all the devices of a segment:
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// 1 (bus) x 32 (devices) x 8 (functions) = 256
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// Note: Currently only 1 bus is supported in a segment.
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iort.write(mapping_offset + 4, (255_u32).to_le());
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// The lowest value in the output range
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iort.write(mapping_offset + 8, ((256 * segment.id) as u32).to_le());
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// id_mapping_array_output_reference should be
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// the ITS group node (the first node) if no SMMU
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iort.write(mapping_offset + 12, (48u32).to_le());
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// Flags
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iort.write(mapping_offset + 16, (0u32).to_le());
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}
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iort.update_checksum();
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iort
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}
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fn create_viot_table(iommu_bdf: &PciBdf, devices_bdf: &[PciBdf]) -> Sdt {
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// VIOT
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let mut viot = Sdt::new(*b"VIOT", 36, 0, *b"CLOUDH", *b"CHVIOT ", 0);
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// Node count
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viot.append((devices_bdf.len() + 1) as u16);
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// Node offset
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viot.append(48u16);
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// VIOT reserved 8 bytes
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viot.append_slice(&[0u8; 8]);
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// Virtio-iommu based on virtio-pci node
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viot.append(ViotVirtioPciNode {
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type_: 3,
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length: 16,
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pci_segment: iommu_bdf.segment(),
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pci_bdf_number: iommu_bdf.into(),
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..Default::default()
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});
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|
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for device_bdf in devices_bdf {
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viot.append(ViotPciRangeNode {
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type_: 1,
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length: 24,
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endpoint_start: device_bdf.into(),
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pci_segment_start: device_bdf.segment(),
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pci_segment_end: device_bdf.segment(),
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pci_bdf_start: device_bdf.into(),
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pci_bdf_end: device_bdf.into(),
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output_node: 48,
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..Default::default()
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});
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}
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viot
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}
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pub fn create_acpi_tables(
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guest_mem: &GuestMemoryMmap,
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device_manager: &Arc<Mutex<DeviceManager>>,
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cpu_manager: &Arc<Mutex<CpuManager>>,
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memory_manager: &Arc<Mutex<MemoryManager>>,
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numa_nodes: &NumaNodes,
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) -> GuestAddress {
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let start_time = Instant::now();
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let rsdp_offset = arch::layout::RSDP_POINTER;
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let mut tables: Vec<u64> = Vec::new();
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|
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// DSDT
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let dsdt = create_dsdt_table(device_manager, cpu_manager, memory_manager);
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let dsdt_offset = rsdp_offset.checked_add(Rsdp::len() as u64).unwrap();
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guest_mem
|
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.write_slice(dsdt.as_slice(), dsdt_offset)
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.expect("Error writing DSDT table");
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|
|
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// FACP aka FADT
|
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let facp = create_facp_table(dsdt_offset);
|
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let facp_offset = dsdt_offset.checked_add(dsdt.len() as u64).unwrap();
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guest_mem
|
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.write_slice(facp.as_slice(), facp_offset)
|
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.expect("Error writing FACP table");
|
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tables.push(facp_offset.0);
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// MADT
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let madt = cpu_manager.lock().unwrap().create_madt();
|
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let madt_offset = facp_offset.checked_add(facp.len() as u64).unwrap();
|
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guest_mem
|
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.write_slice(madt.as_slice(), madt_offset)
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.expect("Error writing MADT table");
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tables.push(madt_offset.0);
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let mut prev_tbl_len = madt.len() as u64;
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let mut prev_tbl_off = madt_offset;
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|
|
// PPTT
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|
#[cfg(target_arch = "aarch64")]
|
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{
|
|
let pptt = cpu_manager.lock().unwrap().create_pptt();
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|
let pptt_offset = prev_tbl_off.checked_add(prev_tbl_len).unwrap();
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guest_mem
|
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.write_slice(pptt.as_slice(), pptt_offset)
|
|
.expect("Error writing PPTT table");
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|
tables.push(pptt_offset.0);
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prev_tbl_len = pptt.len() as u64;
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|
prev_tbl_off = pptt_offset;
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}
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// GTDT
|
|
#[cfg(target_arch = "aarch64")]
|
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{
|
|
let gtdt = create_gtdt_table();
|
|
let gtdt_offset = prev_tbl_off.checked_add(prev_tbl_len).unwrap();
|
|
guest_mem
|
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.write_slice(gtdt.as_slice(), gtdt_offset)
|
|
.expect("Error writing GTDT table");
|
|
tables.push(gtdt_offset.0);
|
|
prev_tbl_len = gtdt.len() as u64;
|
|
prev_tbl_off = gtdt_offset;
|
|
}
|
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|
|
// MCFG
|
|
let mcfg = create_mcfg_table(device_manager.lock().unwrap().pci_segments());
|
|
let mcfg_offset = prev_tbl_off.checked_add(prev_tbl_len).unwrap();
|
|
guest_mem
|
|
.write_slice(mcfg.as_slice(), mcfg_offset)
|
|
.expect("Error writing MCFG table");
|
|
tables.push(mcfg_offset.0);
|
|
prev_tbl_len = mcfg.len() as u64;
|
|
prev_tbl_off = mcfg_offset;
|
|
|
|
// SPCR and DBG2
|
|
#[cfg(target_arch = "aarch64")]
|
|
{
|
|
let is_serial_on = device_manager
|
|
.lock()
|
|
.unwrap()
|
|
.get_device_info()
|
|
.clone()
|
|
.get(&(DeviceType::Serial, DeviceType::Serial.to_string()))
|
|
.is_some();
|
|
let serial_device_addr = arch::layout::LEGACY_SERIAL_MAPPED_IO_START;
|
|
let serial_device_irq = if is_serial_on {
|
|
device_manager
|
|
.lock()
|
|
.unwrap()
|
|
.get_device_info()
|
|
.clone()
|
|
.get(&(DeviceType::Serial, DeviceType::Serial.to_string()))
|
|
.unwrap()
|
|
.irq()
|
|
} else {
|
|
// If serial is turned off, add a fake device with invalid irq.
|
|
31
|
|
};
|
|
|
|
// SPCR
|
|
let spcr = create_spcr_table(serial_device_addr, serial_device_irq);
|
|
let spcr_offset = prev_tbl_off.checked_add(prev_tbl_len).unwrap();
|
|
guest_mem
|
|
.write_slice(spcr.as_slice(), spcr_offset)
|
|
.expect("Error writing SPCR table");
|
|
tables.push(spcr_offset.0);
|
|
prev_tbl_len = spcr.len() as u64;
|
|
prev_tbl_off = spcr_offset;
|
|
|
|
// DBG2
|
|
let dbg2 = create_dbg2_table(serial_device_addr);
|
|
let dbg2_offset = prev_tbl_off.checked_add(prev_tbl_len).unwrap();
|
|
guest_mem
|
|
.write_slice(dbg2.as_slice(), dbg2_offset)
|
|
.expect("Error writing DBG2 table");
|
|
tables.push(dbg2_offset.0);
|
|
prev_tbl_len = dbg2.len() as u64;
|
|
prev_tbl_off = dbg2_offset;
|
|
}
|
|
|
|
// SRAT and SLIT
|
|
// Only created if the NUMA nodes list is not empty.
|
|
if !numa_nodes.is_empty() {
|
|
// SRAT
|
|
let srat = create_srat_table(numa_nodes);
|
|
let srat_offset = prev_tbl_off.checked_add(prev_tbl_len).unwrap();
|
|
guest_mem
|
|
.write_slice(srat.as_slice(), srat_offset)
|
|
.expect("Error writing SRAT table");
|
|
tables.push(srat_offset.0);
|
|
|
|
// SLIT
|
|
let slit = create_slit_table(numa_nodes);
|
|
let slit_offset = srat_offset.checked_add(srat.len() as u64).unwrap();
|
|
guest_mem
|
|
.write_slice(slit.as_slice(), slit_offset)
|
|
.expect("Error writing SRAT table");
|
|
tables.push(slit_offset.0);
|
|
|
|
prev_tbl_len = slit.len() as u64;
|
|
prev_tbl_off = slit_offset;
|
|
};
|
|
|
|
#[cfg(target_arch = "aarch64")]
|
|
{
|
|
let iort = create_iort_table(device_manager.lock().unwrap().pci_segments());
|
|
let iort_offset = prev_tbl_off.checked_add(prev_tbl_len).unwrap();
|
|
guest_mem
|
|
.write_slice(iort.as_slice(), iort_offset)
|
|
.expect("Error writing IORT table");
|
|
tables.push(iort_offset.0);
|
|
prev_tbl_len = iort.len() as u64;
|
|
prev_tbl_off = iort_offset;
|
|
}
|
|
|
|
// VIOT
|
|
if let Some((iommu_bdf, devices_bdf)) = device_manager.lock().unwrap().iommu_attached_devices()
|
|
{
|
|
let viot = create_viot_table(iommu_bdf, devices_bdf);
|
|
|
|
let viot_offset = prev_tbl_off.checked_add(prev_tbl_len).unwrap();
|
|
guest_mem
|
|
.write_slice(viot.as_slice(), viot_offset)
|
|
.expect("Error writing VIOT table");
|
|
tables.push(viot_offset.0);
|
|
prev_tbl_len = viot.len() as u64;
|
|
prev_tbl_off = viot_offset;
|
|
}
|
|
|
|
// XSDT
|
|
let mut xsdt = Sdt::new(*b"XSDT", 36, 1, *b"CLOUDH", *b"CHXSDT ", 1);
|
|
for table in tables {
|
|
xsdt.append(table);
|
|
}
|
|
xsdt.update_checksum();
|
|
let xsdt_offset = prev_tbl_off.checked_add(prev_tbl_len).unwrap();
|
|
guest_mem
|
|
.write_slice(xsdt.as_slice(), xsdt_offset)
|
|
.expect("Error writing XSDT table");
|
|
|
|
// RSDP
|
|
let rsdp = Rsdp::new(*b"CLOUDH", xsdt_offset.0);
|
|
guest_mem
|
|
.write_slice(rsdp.as_slice(), rsdp_offset)
|
|
.expect("Error writing RSDP");
|
|
|
|
info!(
|
|
"Generated ACPI tables: took {}µs",
|
|
Instant::now().duration_since(start_time).as_micros()
|
|
);
|
|
rsdp_offset
|
|
}
|
|
|
|
#[cfg(feature = "tdx")]
|
|
pub fn create_acpi_tables_tdx(
|
|
device_manager: &Arc<Mutex<DeviceManager>>,
|
|
cpu_manager: &Arc<Mutex<CpuManager>>,
|
|
memory_manager: &Arc<Mutex<MemoryManager>>,
|
|
numa_nodes: &NumaNodes,
|
|
) -> Vec<Sdt> {
|
|
// DSDT
|
|
let mut tables = vec![create_dsdt_table(
|
|
device_manager,
|
|
cpu_manager,
|
|
memory_manager,
|
|
)];
|
|
|
|
// FACP aka FADT
|
|
tables.push(create_facp_table(GuestAddress(0)));
|
|
|
|
// MADT
|
|
tables.push(cpu_manager.lock().unwrap().create_madt());
|
|
|
|
// MCFG
|
|
tables.push(create_mcfg_table(
|
|
device_manager.lock().unwrap().pci_segments(),
|
|
));
|
|
|
|
// SRAT and SLIT
|
|
// Only created if the NUMA nodes list is not empty.
|
|
if !numa_nodes.is_empty() {
|
|
// SRAT
|
|
tables.push(create_srat_table(numa_nodes));
|
|
|
|
// SLIT
|
|
tables.push(create_slit_table(numa_nodes));
|
|
};
|
|
|
|
// VIOT
|
|
if let Some((iommu_bdf, devices_bdf)) = device_manager.lock().unwrap().iommu_attached_devices()
|
|
{
|
|
tables.push(create_viot_table(iommu_bdf, devices_bdf));
|
|
}
|
|
|
|
tables
|
|
}
|