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3e482c9c74
When running TDX guest, the Guest Physical Address space is limited by a shared bit that is located on bit 47 for 4 level paging, and on bit 51 for 5 level paging (when GPAW bit is 1). In order to keep things simple, and since a 47 bits address space is 128TiB large, we ensure to limit the physical addressable space to 47 bits when runnning TDX. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>