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As mentioned in the PCI specification: If a dedicated Base Address register is not feasible, it is recommended that a function isolate the MSI-X structures from the non-MSI-X structures with aligned 8 KB ranges rather than the mandatory aligned 4 KB ranges. That's why this patch ensures that each structure present on the BAR is 8KiB aligned. It also fixes the MSI-X table and PBA sizes so that they can support up to 2048 vectors, as specified for MSI-X. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com> |
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