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https://github.com/cloud-hypervisor/cloud-hypervisor.git
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4d98dcb077
As mentioned in the PCI specification, the Function Mask from the Message Control Register can be set to prevent a device from injecting MSI-X messages. This supersedes the vector masking as it interacts at the device level. Here quoted from the specification: For MSI and MSI-X, while a vector is masked, the function is prohibited from sending the associated message, and the function must set the associated Pending bit whenever the function would otherwise send the message. When software unmasks a vector whose associated Pending bit is set, the function must schedule sending the associated message, and clear the Pending bit as soon as the message has been sent. Note that clearing the MSI-X Function Mask bit may result in many messages needing to be sent. This commit implements the behavior described above by reorganizing the way the PCI configuration space is being written. It is indeed important to be able to catch a change in the Message Control Register without having to implement it for every PciDevice implementation. Instead, the PciConfiguration has been modified to take care of handling any update made to this register. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
338 lines
11 KiB
Rust
338 lines
11 KiB
Rust
// Copyright © 2019 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
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//
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extern crate byteorder;
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extern crate vm_memory;
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use std::sync::Arc;
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use crate::device::InterruptParameters;
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use crate::{InterruptDelivery, PciCapability, PciCapabilityID};
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use byteorder::{ByteOrder, LittleEndian};
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use vm_memory::ByteValued;
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const MAX_MSIX_VECTORS_PER_DEVICE: u16 = 2048;
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const MSIX_TABLE_ENTRIES_MODULO: u64 = 16;
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const MSIX_PBA_ENTRIES_MODULO: u64 = 8;
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const BITS_PER_PBA_ENTRY: usize = 64;
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const FUNCTION_MASK_BIT: u8 = 14;
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#[derive(Debug, Clone)]
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pub struct MsixTableEntry {
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pub msg_addr_lo: u32,
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pub msg_addr_hi: u32,
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pub msg_data: u32,
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pub vector_ctl: u32,
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}
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impl MsixTableEntry {
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pub fn is_masked(&self) -> bool {
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self.vector_ctl == 1u32
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}
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}
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impl Default for MsixTableEntry {
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fn default() -> Self {
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MsixTableEntry {
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msg_addr_lo: 0,
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msg_addr_hi: 0,
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msg_data: 0,
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vector_ctl: 0,
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}
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}
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}
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pub struct MsixConfig {
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pub table_entries: Vec<MsixTableEntry>,
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pub pba_entries: Vec<u64>,
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interrupt_cb: Option<Arc<InterruptDelivery>>,
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masked: bool,
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}
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impl MsixConfig {
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pub fn new(msix_vectors: u16) -> Self {
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assert!(msix_vectors <= MAX_MSIX_VECTORS_PER_DEVICE);
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let mut table_entries: Vec<MsixTableEntry> = Vec::new();
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table_entries.resize_with(msix_vectors as usize, Default::default);
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let mut pba_entries: Vec<u64> = Vec::new();
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let num_pba_entries: usize = ((msix_vectors as usize) / BITS_PER_PBA_ENTRY) + 1;
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pba_entries.resize_with(num_pba_entries, Default::default);
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MsixConfig {
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table_entries,
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pba_entries,
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interrupt_cb: None,
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masked: false,
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}
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}
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pub fn register_interrupt_cb(&mut self, cb: Arc<InterruptDelivery>) {
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self.interrupt_cb = Some(cb);
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}
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pub fn is_masked(&self) -> bool {
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self.masked
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}
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pub fn set_msg_ctl(&mut self, reg: u16) {
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let old_masked = self.masked;
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self.masked = ((reg >> FUNCTION_MASK_BIT) & 1u16) == 1u16;
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// If the Function Mask bit was set, and has just been cleared, it's
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// important to go through the entire PBA to check if there was any
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// pending MSI-X message to inject, given that the vector is not
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// masked.
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if old_masked && !self.masked {
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for (index, entry) in self.table_entries.clone().iter().enumerate() {
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if !entry.is_masked() && self.get_pba_bit(index as u16) == 1 {
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self.inject_msix_and_clear_pba(index);
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}
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}
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}
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}
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pub fn read_table(&mut self, offset: u64, data: &mut [u8]) {
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assert!((data.len() == 4 || data.len() == 8));
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let index: usize = (offset / MSIX_TABLE_ENTRIES_MODULO) as usize;
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let modulo_offset = offset % MSIX_TABLE_ENTRIES_MODULO;
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match data.len() {
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4 => {
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let value = match modulo_offset {
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0x0 => self.table_entries[index].msg_addr_lo,
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0x4 => self.table_entries[index].msg_addr_hi,
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0x8 => self.table_entries[index].msg_data,
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0x10 => self.table_entries[index].vector_ctl,
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_ => {
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error!("invalid offset");
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0
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}
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};
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debug!("MSI_R TABLE offset 0x{:x} data 0x{:x}", offset, value);
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LittleEndian::write_u32(data, value);
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}
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8 => {
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let value = match modulo_offset {
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0x0 => {
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(u64::from(self.table_entries[index].msg_addr_hi) << 32)
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| u64::from(self.table_entries[index].msg_addr_lo)
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}
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0x8 => {
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(u64::from(self.table_entries[index].vector_ctl) << 32)
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| u64::from(self.table_entries[index].msg_data)
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}
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_ => {
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error!("invalid offset");
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0
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}
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};
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debug!("MSI_R TABLE offset 0x{:x} data 0x{:x}", offset, value);
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LittleEndian::write_u64(data, value);
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}
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_ => {
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error!("invalid data length");
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}
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}
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}
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pub fn write_table(&mut self, offset: u64, data: &[u8]) {
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assert!((data.len() == 4 || data.len() == 8));
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let index: usize = (offset / MSIX_TABLE_ENTRIES_MODULO) as usize;
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let modulo_offset = offset % MSIX_TABLE_ENTRIES_MODULO;
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// Store the value of the entry before modification
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let mut old_entry: Option<MsixTableEntry> = None;
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match data.len() {
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4 => {
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let value = LittleEndian::read_u32(data);
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match modulo_offset {
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0x0 => self.table_entries[index].msg_addr_lo = value,
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0x4 => self.table_entries[index].msg_addr_hi = value,
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0x8 => self.table_entries[index].msg_data = value,
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0x10 => {
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old_entry = Some(self.table_entries[index].clone());
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self.table_entries[index].vector_ctl = value;
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}
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_ => error!("invalid offset"),
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};
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debug!("MSI_W TABLE offset 0x{:x} data 0x{:x}", offset, value);
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}
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8 => {
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let value = LittleEndian::read_u64(data);
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match modulo_offset {
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0x0 => {
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self.table_entries[index].msg_addr_lo = (value & 0xffff_ffffu64) as u32;
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self.table_entries[index].msg_addr_hi = (value >> 32) as u32;
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}
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0x8 => {
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old_entry = Some(self.table_entries[index].clone());
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self.table_entries[index].msg_data = (value & 0xffff_ffffu64) as u32;
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self.table_entries[index].vector_ctl = (value >> 32) as u32;
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}
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_ => error!("invalid offset"),
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};
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debug!("MSI_W TABLE offset 0x{:x} data 0x{:x}", offset, value);
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}
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_ => error!("invalid data length"),
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};
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// After the MSI-X table entry has been updated, it is necessary to
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// check if the vector control masking bit has changed. In case the
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// bit has been flipped from 1 to 0, we need to inject a MSI message
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// if the corresponding pending bit from the PBA is set. Once the MSI
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// has been injected, the pending bit in the PBA needs to be cleared.
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// All of this is valid only if MSI-X has not been masked for the whole
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// device.
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if let Some(old_entry) = old_entry {
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// Check if bit has been flipped
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if !self.is_masked()
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&& old_entry.is_masked()
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&& !self.table_entries[index].is_masked()
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&& self.get_pba_bit(index as u16) == 1
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{
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self.inject_msix_and_clear_pba(index);
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}
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}
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}
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pub fn read_pba(&mut self, offset: u64, data: &mut [u8]) {
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assert!((data.len() == 4 || data.len() == 8));
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let index: usize = (offset / MSIX_PBA_ENTRIES_MODULO) as usize;
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let modulo_offset = offset % MSIX_PBA_ENTRIES_MODULO;
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match data.len() {
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4 => {
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let value: u32 = match modulo_offset {
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0x0 => (self.pba_entries[index] & 0xffff_ffffu64) as u32,
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0x4 => (self.pba_entries[index] >> 32) as u32,
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_ => {
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error!("invalid offset");
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0
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}
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};
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debug!("MSI_R PBA offset 0x{:x} data 0x{:x}", offset, value);
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LittleEndian::write_u32(data, value);
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}
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8 => {
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let value: u64 = match modulo_offset {
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0x0 => self.pba_entries[index],
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_ => {
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error!("invalid offset");
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0
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}
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};
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debug!("MSI_R PBA offset 0x{:x} data 0x{:x}", offset, value);
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LittleEndian::write_u64(data, value);
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}
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_ => {
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error!("invalid data length");
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}
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}
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}
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pub fn write_pba(&mut self, _offset: u64, _data: &[u8]) {
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error!("Pending Bit Array is read only");
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}
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pub fn set_pba_bit(&mut self, vector: u16, reset: bool) {
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assert!(vector < MAX_MSIX_VECTORS_PER_DEVICE);
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let index: usize = (vector as usize) / BITS_PER_PBA_ENTRY;
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let shift: usize = (vector as usize) % BITS_PER_PBA_ENTRY;
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let mut mask: u64 = (1 << shift) as u64;
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if reset {
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mask = !mask;
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self.pba_entries[index] &= mask;
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} else {
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self.pba_entries[index] |= mask;
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}
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}
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fn get_pba_bit(&self, vector: u16) -> u8 {
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assert!(vector < MAX_MSIX_VECTORS_PER_DEVICE);
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let index: usize = (vector as usize) / BITS_PER_PBA_ENTRY;
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let shift: usize = (vector as usize) % BITS_PER_PBA_ENTRY;
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((self.pba_entries[index] >> shift) & 0x0000_0001u64) as u8
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}
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fn inject_msix_and_clear_pba(&mut self, vector: usize) {
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// Inject the MSI message
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if let Some(cb) = &self.interrupt_cb {
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match (cb)(InterruptParameters {
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msix: Some(&self.table_entries[vector]),
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}) {
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Ok(_) => debug!("MSI-X injected on vector control flip"),
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Err(e) => error!("failed to inject MSI-X: {}", e),
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};
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}
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// Clear the bit from PBA
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self.set_pba_bit(vector as u16, true);
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}
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}
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#[allow(dead_code)]
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#[repr(packed)]
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#[derive(Clone, Copy, Default)]
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pub struct MsixCap {
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// Message Control Register
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// 10-0: MSI-X Table size
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// 13-11: Reserved
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// 14: Mask. Mask all MSI-X when set.
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// 15: Enable. Enable all MSI-X when set.
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msg_ctl: u16,
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// Table. Contains the offset and the BAR indicator (BIR)
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// 2-0: Table BAR indicator (BIR). Can be 0 to 5.
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// 31-3: Table offset in the BAR pointed by the BIR.
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table: u32,
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// Pending Bit Array. Contains the offset and the BAR indicator (BIR)
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// 2-0: PBA BAR indicator (BIR). Can be 0 to 5.
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// 31-3: PBA offset in the BAR pointed by the BIR.
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pba: u32,
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}
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// It is safe to implement ByteValued. All members are simple numbers and any value is valid.
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unsafe impl ByteValued for MsixCap {}
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impl PciCapability for MsixCap {
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fn bytes(&self) -> &[u8] {
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self.as_slice()
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}
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fn id(&self) -> PciCapabilityID {
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PciCapabilityID::MSIX
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}
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}
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impl MsixCap {
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pub fn new(pci_bar: u8, table_size: u16, table_off: u32, pba_off: u32) -> Self {
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assert!(table_size < MAX_MSIX_VECTORS_PER_DEVICE);
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// Set the table size and enable MSI-X.
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let msg_ctl: u16 = 0x8000u16 + table_size - 1;
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MsixCap {
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msg_ctl,
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table: (table_off & 0xffff_fff8u32) | u32::from(pci_bar & 0x7u8),
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pba: (pba_off & 0xffff_fff8u32) | u32::from(pci_bar & 0x7u8),
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}
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}
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}
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