mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
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b5bcdbaf48
As the first step to complete live-migration with tracking dirty-pages written by the VMM, this commit patches the dependent vm-memory crate to the upstream version with the dirty-page-tracking capability. Most changes are due to the updated `GuestMemoryMmap`, `GuestRegionMmap`, and `MmapRegion` structs which are taking an additional generic type parameter to specify what 'bitmap backend' is used. The above changes should be transparent to the rest of the code base, e.g. all unit/integration tests should pass without additional changes. Signed-off-by: Bo Chen <chen.bo@intel.com>
82 lines
3.0 KiB
Rust
82 lines
3.0 KiB
Rust
// Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the THIRD-PARTY file.
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use super::get_fdt_addr;
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use crate::GuestMemoryMmap;
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use hypervisor::kvm::kvm_bindings::{
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kvm_regs, user_pt_regs, KVM_REG_ARM64, KVM_REG_ARM_CORE, KVM_REG_SIZE_U64,
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};
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use hypervisor::{arm64_core_reg_id, offset__of};
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use std::sync::Arc;
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use std::{mem, result};
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/// Errors thrown while setting aarch64 registers.
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#[derive(Debug)]
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pub enum Error {
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/// Failed to set core register (PC, PSTATE or general purpose ones).
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SetCoreRegister(hypervisor::HypervisorCpuError),
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/// Failed to get a system register.
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GetSysRegister(hypervisor::HypervisorCpuError),
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}
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type Result<T> = result::Result<T, Error>;
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#[allow(non_upper_case_globals)]
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// PSR (Processor State Register) bits.
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// Taken from arch/arm64/include/uapi/asm/ptrace.h.
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const PSR_MODE_EL1h: u64 = 0x0000_0005;
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const PSR_F_BIT: u64 = 0x0000_0040;
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const PSR_I_BIT: u64 = 0x0000_0080;
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const PSR_A_BIT: u64 = 0x0000_0100;
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const PSR_D_BIT: u64 = 0x0000_0200;
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// Taken from arch/arm64/kvm/inject_fault.c.
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const PSTATE_FAULT_BITS_64: u64 = PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | PSR_I_BIT | PSR_D_BIT;
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/// Configure core registers for a given CPU.
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///
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/// # Arguments
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///
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/// * `vcpu` - Structure for the VCPU that holds the VCPU's fd.
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/// * `cpu_id` - Index of current vcpu.
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/// * `boot_ip` - Starting instruction pointer.
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/// * `mem` - Reserved DRAM for current VM.
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pub fn setup_regs(
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vcpu: &Arc<dyn hypervisor::Vcpu>,
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cpu_id: u8,
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boot_ip: u64,
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_mem: &GuestMemoryMmap,
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) -> Result<()> {
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let kreg_off = offset__of!(kvm_regs, regs);
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// Get the register index of the PSTATE (Processor State) register.
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let pstate = offset__of!(user_pt_regs, pstate) + kreg_off;
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vcpu.set_reg(
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arm64_core_reg_id!(KVM_REG_SIZE_U64, pstate),
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PSTATE_FAULT_BITS_64,
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)
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.map_err(Error::SetCoreRegister)?;
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// Other vCPUs are powered off initially awaiting PSCI wakeup.
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if cpu_id == 0 {
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// Setting the PC (Processor Counter) to the current program address (kernel address).
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let pc = offset__of!(user_pt_regs, pc) + kreg_off;
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vcpu.set_reg(arm64_core_reg_id!(KVM_REG_SIZE_U64, pc), boot_ip as u64)
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.map_err(Error::SetCoreRegister)?;
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// Last mandatory thing to set -> the address pointing to the FDT (also called DTB).
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// "The device tree blob (dtb) must be placed on an 8-byte boundary and must
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// not exceed 2 megabytes in size." -> https://www.kernel.org/doc/Documentation/arm64/booting.txt.
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// We are choosing to place it the end of DRAM. See `get_fdt_addr`.
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let regs0 = offset__of!(user_pt_regs, regs) + kreg_off;
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vcpu.set_reg(
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arm64_core_reg_id!(KVM_REG_SIZE_U64, regs0),
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get_fdt_addr() as u64,
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)
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.map_err(Error::SetCoreRegister)?;
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}
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Ok(())
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}
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