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95f83320b1
This doesn't need to be rendered in the HTML API documentation, and wouldn't be formatted correctly if it was. Signed-off-by: Alyssa Ross <hi@alyssa.is>
44 lines
1.7 KiB
Rust
44 lines
1.7 KiB
Rust
// Copyright 2022 Arm Limited (or its affiliates). All rights reserved.
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// SPDX-License-Identifier: Apache-2.0
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// AArch64 system register encoding:
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// See https://developer.arm.com/documentation/ddi0487 (chapter D12)
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//
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// 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
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// +----------+---+-----+-----+-----+-----+-----+----+
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// |1101010100| L | op0 | op1 | CRn | CRm | op2 | Rt |
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// +----------+---+-----+-----+-----+-----+-----+----+
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//
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// Notes:
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// - L and Rt are reserved as implementation defined fields, ignored.
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const SYSREG_HEAD: u32 = 0b1101010100u32 << 22;
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const SYSREG_OP0_SHIFT: u32 = 19;
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const SYSREG_OP0_MASK: u32 = 0b11u32 << 19;
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const SYSREG_OP1_SHIFT: u32 = 16;
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const SYSREG_OP1_MASK: u32 = 0b111u32 << 16;
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const SYSREG_CRN_SHIFT: u32 = 12;
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const SYSREG_CRN_MASK: u32 = 0b1111u32 << 12;
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const SYSREG_CRM_SHIFT: u32 = 8;
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const SYSREG_CRM_MASK: u32 = 0b1111u32 << 8;
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const SYSREG_OP2_SHIFT: u32 = 5;
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const SYSREG_OP2_MASK: u32 = 0b111u32 << 5;
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/// Define the ID of system registers
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#[macro_export]
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macro_rules! arm64_sys_reg {
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($name: tt, $op0: tt, $op1: tt, $crn: tt, $crm: tt, $op2: tt) => {
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pub const $name: u32 = SYSREG_HEAD
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| ((($op0 as u32) << SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK as u32)
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| ((($op1 as u32) << SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK as u32)
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| ((($crn as u32) << SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK as u32)
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| ((($crm as u32) << SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK as u32)
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| ((($op2 as u32) << SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK as u32);
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};
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}
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arm64_sys_reg!(MPIDR_EL1, 3, 0, 0, 0, 5);
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arm64_sys_reg!(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0);
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arm64_sys_reg!(TTBR1_EL1, 3, 0, 2, 0, 1);
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arm64_sys_reg!(TCR_EL1, 3, 0, 2, 0, 2);
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