mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
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467 lines
15 KiB
Rust
467 lines
15 KiB
Rust
// Copyright 2019 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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//
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// Copyright © 2019 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
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//
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// Implementation of an intel 82093AA Input/Output Advanced Programmable Interrupt Controller
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// See https://pdos.csail.mit.edu/6.828/2016/readings/ia32/ioapic.pdf for a specification.
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use crate::BusDevice;
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use anyhow::anyhow;
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use byteorder::{ByteOrder, LittleEndian};
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use std::io;
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use std::result;
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use std::sync::Arc;
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use vm_device::interrupt::{
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InterruptIndex, InterruptManager, InterruptSourceConfig, InterruptSourceGroup,
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MsiIrqGroupConfig, MsiIrqSourceConfig,
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};
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use vm_memory::GuestAddress;
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use vm_migration::{
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Migratable, MigratableError, Pausable, Snapshot, SnapshotDataSection, Snapshottable,
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Transportable,
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};
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#[derive(Serialize, Deserialize)]
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#[serde(remote = "GuestAddress")]
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pub struct GuestAddressDef(pub u64);
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#[derive(Debug)]
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pub enum Error {
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/// Invalid destination mode.
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InvalidDestinationMode,
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/// Invalid trigger mode.
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InvalidTriggerMode,
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/// Invalid delivery mode.
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InvalidDeliveryMode,
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/// Failed creating the interrupt source group.
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CreateInterruptSourceGroup(io::Error),
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/// Failed triggering the interrupt.
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TriggerInterrupt(io::Error),
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/// Failed masking the interrupt.
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MaskInterrupt(io::Error),
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/// Failed unmasking the interrupt.
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UnmaskInterrupt(io::Error),
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/// Failed updating the interrupt.
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UpdateInterrupt(io::Error),
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/// Failed enabling the interrupt.
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EnableInterrupt(io::Error),
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}
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type Result<T> = result::Result<T, Error>;
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// I/O REDIRECTION TABLE REGISTER
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//
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// There are 24 I/O Redirection Table entry registers. Each register is a
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// dedicated entry for each interrupt input signal. Each register is 64 bits
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// split between two 32 bits registers as follow:
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//
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// 63-56: Destination Field - R/W
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// 55-17: Reserved
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// 16: Interrupt Mask - R/W
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// 15: Trigger Mode - R/W
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// 14: Remote IRR - RO
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// 13: Interrupt Input Pin Polarity - R/W
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// 12: Delivery Status - RO
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// 11: Destination Mode - R/W
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// 10-8: Delivery Mode - R/W
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// 7-0: Interrupt Vector - R/W
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pub type RedirectionTableEntry = u64;
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fn vector(entry: RedirectionTableEntry) -> u8 {
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(entry & 0xffu64) as u8
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}
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fn delivery_mode(entry: RedirectionTableEntry) -> u8 {
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((entry >> 8) & 0x7u64) as u8
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}
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fn destination_mode(entry: RedirectionTableEntry) -> u8 {
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((entry >> 11) & 0x1u64) as u8
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}
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fn remote_irr(entry: RedirectionTableEntry) -> u8 {
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((entry >> 14) & 0x1u64) as u8
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}
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fn trigger_mode(entry: RedirectionTableEntry) -> u8 {
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((entry >> 15) & 0x1u64) as u8
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}
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fn interrupt_mask(entry: RedirectionTableEntry) -> u8 {
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((entry >> 16) & 0x1u64) as u8
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}
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fn destination_field_physical(entry: RedirectionTableEntry) -> u8 {
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((entry >> 56) & 0xfu64) as u8
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}
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fn destination_field_logical(entry: RedirectionTableEntry) -> u8 {
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((entry >> 56) & 0xffu64) as u8
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}
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fn set_delivery_status(entry: &mut RedirectionTableEntry, val: u8) {
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// Clear bit 12
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*entry &= 0xffff_ffff_ffff_efff;
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// Set it with the expected value
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*entry |= u64::from(val & 0x1) << 12;
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}
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fn set_remote_irr(entry: &mut RedirectionTableEntry, val: u8) {
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// Clear bit 14
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*entry &= 0xffff_ffff_ffff_bfff;
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// Set it with the expected value
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*entry |= u64::from(val & 0x1) << 14;
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}
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pub const NUM_IOAPIC_PINS: usize = 24;
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const IOAPIC_VERSION_ID: u32 = 0x0017_0011;
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// Constants for IOAPIC direct register offset
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const IOAPIC_REG_ID: u8 = 0x00;
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const IOAPIC_REG_VERSION: u8 = 0x01;
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const IOAPIC_REG_ARBITRATION_ID: u8 = 0x02;
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// Register offsets
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const IOREGSEL_OFF: u8 = 0x0;
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const IOWIN_OFF: u8 = 0x10;
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const IOWIN_SCALE: u8 = 0x2;
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const REG_MAX_OFFSET: u8 = IOWIN_OFF + (NUM_IOAPIC_PINS as u8 * 2) - 1;
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#[repr(u8)]
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enum DestinationMode {
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Physical = 0,
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Logical = 1,
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}
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#[repr(u8)]
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enum TriggerMode {
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Edge = 0,
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Level = 1,
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}
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#[repr(u8)]
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enum DeliveryMode {
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Fixed = 0b000,
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Lowest = 0b001,
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SMI = 0b010, // System management interrupt
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RemoteRead = 0b011, // This is no longer supported by intel.
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NMI = 0b100, // Non maskable interrupt
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Init = 0b101,
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Startup = 0b110,
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External = 0b111,
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}
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/// Given an offset that was read from/written to, return a tuple of the relevant IRQ and whether
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/// the offset refers to the high bits of that register.
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fn decode_irq_from_selector(selector: u8) -> (usize, bool) {
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(
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((selector - IOWIN_OFF) / IOWIN_SCALE) as usize,
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selector & 1 != 0,
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)
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}
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pub struct Ioapic {
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id: u32,
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reg_sel: u32,
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reg_entries: [RedirectionTableEntry; NUM_IOAPIC_PINS],
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used_entries: [bool; NUM_IOAPIC_PINS],
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apic_address: GuestAddress,
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interrupt_source_group: Arc<Box<dyn InterruptSourceGroup>>,
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}
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#[derive(Serialize, Deserialize)]
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pub struct IoapicState {
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id: u32,
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reg_sel: u32,
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reg_entries: [RedirectionTableEntry; NUM_IOAPIC_PINS],
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used_entries: [bool; NUM_IOAPIC_PINS],
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#[serde(with = "GuestAddressDef")]
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apic_address: GuestAddress,
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}
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impl BusDevice for Ioapic {
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fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
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assert!(data.len() == 4);
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debug!("IOAPIC_R @ offset 0x{:x}", offset);
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let value: u32 = match offset as u8 {
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IOREGSEL_OFF => self.reg_sel,
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IOWIN_OFF => self.ioapic_read(),
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_ => {
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error!("IOAPIC: failed reading at offset {}", offset);
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return;
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}
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};
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LittleEndian::write_u32(data, value);
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}
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fn write(&mut self, _base: u64, offset: u64, data: &[u8]) {
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assert!(data.len() == 4);
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debug!("IOAPIC_W @ offset 0x{:x}", offset);
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let value = LittleEndian::read_u32(data);
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match offset as u8 {
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IOREGSEL_OFF => self.reg_sel = value,
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IOWIN_OFF => self.ioapic_write(value),
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_ => {
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error!("IOAPIC: failed writing at offset {}", offset);
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}
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}
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}
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}
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impl Ioapic {
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pub fn new(
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apic_address: GuestAddress,
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interrupt_manager: Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
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) -> Result<Ioapic> {
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let interrupt_source_group = interrupt_manager
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.create_group(MsiIrqGroupConfig {
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base: 0 as InterruptIndex,
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count: NUM_IOAPIC_PINS as InterruptIndex,
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})
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.map_err(Error::CreateInterruptSourceGroup)?;
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interrupt_source_group
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.enable()
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.map_err(Error::EnableInterrupt)?;
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Ok(Ioapic {
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id: 0,
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reg_sel: 0,
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reg_entries: [0; NUM_IOAPIC_PINS],
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used_entries: [false; NUM_IOAPIC_PINS],
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apic_address,
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interrupt_source_group,
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})
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}
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// The ioapic must be informed about EOIs in order to deassert interrupts
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// already sent.
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pub fn end_of_interrupt(&mut self, vec: u8) {
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for i in 0..NUM_IOAPIC_PINS {
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let entry = &mut self.reg_entries[i];
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// Clear Remote IRR bit
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if vector(*entry) == vec && trigger_mode(*entry) == 1 {
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set_remote_irr(entry, 0);
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}
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}
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}
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// This should be called anytime an interrupt needs to be injected into the
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// running guest.
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pub fn service_irq(&mut self, irq: usize) -> Result<()> {
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let entry = &mut self.reg_entries[irq];
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self.interrupt_source_group
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.trigger(irq as InterruptIndex)
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.map_err(Error::TriggerInterrupt)?;
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debug!("Interrupt successfully delivered");
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// If trigger mode is level sensitive, set the Remote IRR bit.
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// It will be cleared when the EOI is received.
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if trigger_mode(*entry) == 1 {
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set_remote_irr(entry, 1);
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}
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// Clear the Delivery Status bit
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set_delivery_status(entry, 0);
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Ok(())
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}
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fn update_entry(&self, irq: usize) -> Result<()> {
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let entry = self.reg_entries[irq];
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// Validate Destination Mode value, and retrieve Destination ID
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let destination_mode = destination_mode(entry);
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let destination_id: u8 = match destination_mode {
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x if x == DestinationMode::Physical as u8 => destination_field_physical(entry),
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x if x == DestinationMode::Logical as u8 => destination_field_logical(entry),
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_ => return Err(Error::InvalidDestinationMode),
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};
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// When this bit is set, the message is directed to the processor with
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// the lowest interrupt priority among processors that can receive the
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// interrupt.
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let redirection_hint: u8 = 1;
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// Generate MSI message address
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let low_addr: u32 = self.apic_address.0 as u32
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| u32::from(destination_id) << 12
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| u32::from(redirection_hint) << 3
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| u32::from(destination_mode) << 2;
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// Validate Trigger Mode value
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let trigger_mode = trigger_mode(entry);
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match trigger_mode {
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x if (x == TriggerMode::Edge as u8) || (x == TriggerMode::Level as u8) => {}
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_ => return Err(Error::InvalidTriggerMode),
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}
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// Validate Delivery Mode value
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let delivery_mode = delivery_mode(entry);
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match delivery_mode {
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x if (x == DeliveryMode::Fixed as u8)
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|| (x == DeliveryMode::Lowest as u8)
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|| (x == DeliveryMode::SMI as u8)
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|| (x == DeliveryMode::RemoteRead as u8)
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|| (x == DeliveryMode::NMI as u8)
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|| (x == DeliveryMode::Init as u8)
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|| (x == DeliveryMode::Startup as u8)
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|| (x == DeliveryMode::External as u8) => {}
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_ => return Err(Error::InvalidDeliveryMode),
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}
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// Generate MSI message data
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let data: u32 = u32::from(trigger_mode) << 15
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| u32::from(remote_irr(entry)) << 14
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| u32::from(delivery_mode) << 8
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| u32::from(vector(entry));
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let config = MsiIrqSourceConfig {
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high_addr: 0x0,
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low_addr,
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data,
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};
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self.interrupt_source_group
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.update(irq as InterruptIndex, InterruptSourceConfig::MsiIrq(config))
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.map_err(Error::UpdateInterrupt)?;
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if interrupt_mask(entry) == 1 {
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self.interrupt_source_group
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.mask(irq as InterruptIndex)
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.map_err(Error::MaskInterrupt)?;
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} else {
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self.interrupt_source_group
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.unmask(irq as InterruptIndex)
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.map_err(Error::UnmaskInterrupt)?;
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}
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Ok(())
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}
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fn ioapic_write(&mut self, val: u32) {
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debug!("IOAPIC_W reg 0x{:x}, val 0x{:x}", self.reg_sel, val);
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match self.reg_sel as u8 {
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IOAPIC_REG_ID => self.id = (val >> 24) & 0xf,
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IOWIN_OFF..=REG_MAX_OFFSET => {
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let (index, is_high_bits) = decode_irq_from_selector(self.reg_sel as u8);
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if is_high_bits {
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self.reg_entries[index] &= 0xffff_ffff;
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self.reg_entries[index] |= u64::from(val) << 32;
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} else {
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// Ensure not to override read-only bits:
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// - Delivery Status (bit 12)
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// - Remote IRR (bit 14)
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self.reg_entries[index] &= 0xffff_ffff_0000_5000;
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self.reg_entries[index] |= u64::from(val) & 0xffff_afff;
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}
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// The entry must be updated through the interrupt source
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// group.
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if let Err(e) = self.update_entry(index) {
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error!("Failed updating IOAPIC entry: {:?}", e);
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}
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// Store the information this IRQ is now being used.
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self.used_entries[index] = true;
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}
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_ => error!("IOAPIC: invalid write to register offset"),
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}
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}
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fn ioapic_read(&self) -> u32 {
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debug!("IOAPIC_R reg 0x{:x}", self.reg_sel);
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match self.reg_sel as u8 {
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IOAPIC_REG_VERSION => IOAPIC_VERSION_ID,
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IOAPIC_REG_ID | IOAPIC_REG_ARBITRATION_ID => (self.id & 0xf) << 24,
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IOWIN_OFF..=REG_MAX_OFFSET => {
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let (index, is_high_bits) = decode_irq_from_selector(self.reg_sel as u8);
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if is_high_bits {
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(self.reg_entries[index] >> 32) as u32
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} else {
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(self.reg_entries[index] & 0xffff_ffff) as u32
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}
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}
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_ => {
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error!("IOAPIC: invalid read from register offset");
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0
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}
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}
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}
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fn state(&self) -> IoapicState {
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IoapicState {
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id: self.id,
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reg_sel: self.reg_sel,
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reg_entries: self.reg_entries,
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used_entries: self.used_entries,
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apic_address: self.apic_address,
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}
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}
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fn set_state(&mut self, state: &IoapicState) -> Result<()> {
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self.id = state.id;
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self.reg_sel = state.reg_sel;
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self.reg_entries = state.reg_entries;
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self.used_entries = state.used_entries;
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self.apic_address = state.apic_address;
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for (irq, entry) in self.used_entries.iter().enumerate() {
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if *entry {
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self.update_entry(irq)?;
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}
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}
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Ok(())
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}
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}
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const IOAPIC_SNAPSHOT_ID: &str = "ioapic";
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impl Snapshottable for Ioapic {
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fn id(&self) -> String {
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IOAPIC_SNAPSHOT_ID.to_string()
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}
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fn snapshot(&self) -> std::result::Result<Snapshot, MigratableError> {
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let snapshot =
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serde_json::to_vec(&self.state()).map_err(|e| MigratableError::Snapshot(e.into()))?;
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let mut ioapic_snapshot = Snapshot::new(IOAPIC_SNAPSHOT_ID);
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ioapic_snapshot.add_data_section(SnapshotDataSection {
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id: format!("{}-section", IOAPIC_SNAPSHOT_ID),
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snapshot,
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});
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Ok(ioapic_snapshot)
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}
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fn restore(&mut self, snapshot: Snapshot) -> std::result::Result<(), MigratableError> {
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if let Some(ioapic_section) = snapshot
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.snapshot_data
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.get(&format!("{}-section", IOAPIC_SNAPSHOT_ID))
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{
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let ioapic_state = match serde_json::from_slice(&ioapic_section.snapshot) {
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Ok(state) => state,
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Err(error) => {
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return Err(MigratableError::Restore(anyhow!(
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"Could not deserialize IOAPIC {}",
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error
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)))
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}
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};
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return self.set_state(&ioapic_state).map_err(|e| {
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MigratableError::Restore(anyhow!("Could not restore IOAPIC state {:?}", e))
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});
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}
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Err(MigratableError::Restore(anyhow!(
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"Could not find IOAPIC snapshot section"
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)))
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}
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}
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impl Pausable for Ioapic {}
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impl Transportable for Ioapic {}
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impl Migratable for Ioapic {}
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