Sebastien Boeuf 1379abb94b pci: msi: Fix MSG_CTL update through 32 bits write ... If the MSG_CTL is being written from a 32 bits write access, the offset won't be 0x2, but 0x0 instead. That's simply because 32 bits access have to be aligned on each double word. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>		2019-12-04 08:48:17 +01:00
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bus.rs	vmm: Conditionally update ioeventfds for virtio PCI device	2019-10-31 09:30:59 +01:00
configuration.rs	vmm: Conditionally update ioeventfds for virtio PCI device	2019-10-31 09:30:59 +01:00
device.rs	pci: Remove ioeventfds() from PciDevice trait	2019-10-31 09:30:59 +01:00
lib.rs	pci: Remove KVM dependency	2019-10-29 20:09:04 -07:00
msi.rs	pci: msi: Fix MSG_CTL update through 32 bits write	2019-12-04 08:48:17 +01:00
msix.rs	pci: Add MSI-X helper to check if interrupts are enabled	2019-08-08 17:38:47 +01:00