mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
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In this commit we saved the BDF of a PCI device and set it to "devid" in GSI routing entry, because this field is mandatory for GICv3-ITS. Signed-off-by: Michael Zhao <michael.zhao@arm.com>
235 lines
7.0 KiB
Rust
235 lines
7.0 KiB
Rust
// Copyright © 2019 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
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//
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extern crate byteorder;
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extern crate vm_memory;
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use byteorder::{ByteOrder, LittleEndian};
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use std::sync::Arc;
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use vm_device::interrupt::{
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InterruptIndex, InterruptSourceConfig, InterruptSourceGroup, MsiIrqSourceConfig,
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};
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// MSI control masks
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const MSI_CTL_ENABLE: u16 = 0x1;
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const MSI_CTL_MULTI_MSG_ENABLE: u16 = 0x70;
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const MSI_CTL_64_BITS: u16 = 0x80;
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const MSI_CTL_PER_VECTOR: u16 = 0x100;
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// MSI message offsets
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const MSI_MSG_CTL_OFFSET: u64 = 0x2;
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const MSI_MSG_ADDR_LO_OFFSET: u64 = 0x4;
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// MSI message masks
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const MSI_MSG_ADDR_LO_MASK: u32 = 0xffff_fffc;
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pub fn msi_num_enabled_vectors(msg_ctl: u16) -> usize {
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let field = (msg_ctl >> 4) & 0x7;
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if field > 5 {
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return 0;
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}
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1 << field
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}
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#[derive(Clone, Copy, Default)]
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pub struct MsiCap {
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// Message Control Register
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// 0: MSI enable.
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// 3-1; Multiple message capable.
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// 6-4: Multiple message enable.
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// 7: 64 bits address capable.
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// 8: Per-vector masking capable.
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// 15-9: Reserved.
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pub msg_ctl: u16,
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// Message Address (LSB)
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// 1-0: Reserved.
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// 31-2: Message address.
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pub msg_addr_lo: u32,
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// Message Upper Address (MSB)
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// 31-0: Message address.
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pub msg_addr_hi: u32,
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// Message Data
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// 15-0: Message data.
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pub msg_data: u16,
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// Mask Bits
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// 31-0: Mask bits.
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pub mask_bits: u32,
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// Pending Bits
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// 31-0: Pending bits.
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pub pending_bits: u32,
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}
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impl MsiCap {
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fn addr_64_bits(&self) -> bool {
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self.msg_ctl & MSI_CTL_64_BITS == MSI_CTL_64_BITS
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}
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fn per_vector_mask(&self) -> bool {
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self.msg_ctl & MSI_CTL_PER_VECTOR == MSI_CTL_PER_VECTOR
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}
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fn enabled(&self) -> bool {
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self.msg_ctl & MSI_CTL_ENABLE == MSI_CTL_ENABLE
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}
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fn num_enabled_vectors(&self) -> usize {
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msi_num_enabled_vectors(self.msg_ctl)
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}
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fn vector_masked(&self, vector: usize) -> bool {
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if !self.per_vector_mask() {
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return false;
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}
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(self.mask_bits >> vector) & 0x1 == 0x1
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}
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fn size(&self) -> u64 {
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let mut size: u64 = 0xa;
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if self.addr_64_bits() {
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size += 0x4;
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}
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if self.per_vector_mask() {
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size += 0xa;
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}
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size
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}
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fn update(&mut self, offset: u64, data: &[u8]) {
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// Calculate message data offset depending on the address being 32 or
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// 64 bits.
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// Calculate upper address offset if the address is 64 bits.
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// Calculate mask bits offset based on the address being 32 or 64 bits
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// and based on the per vector masking being enabled or not.
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let (msg_data_offset, addr_hi_offset, mask_bits_offset): (u64, Option<u64>, Option<u64>) =
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if self.addr_64_bits() {
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let mask_bits = if self.per_vector_mask() {
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Some(0x10)
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} else {
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None
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};
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(0xc, Some(0x8), mask_bits)
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} else {
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let mask_bits = if self.per_vector_mask() {
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Some(0xc)
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} else {
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None
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};
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(0x8, None, mask_bits)
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};
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// Update cache without overriding the read-only bits.
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match data.len() {
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2 => {
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let value = LittleEndian::read_u16(data);
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match offset {
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MSI_MSG_CTL_OFFSET => {
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self.msg_ctl = (self.msg_ctl & !(MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE))
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| (value & (MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE))
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}
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x if x == msg_data_offset => self.msg_data = value,
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_ => error!("invalid offset"),
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}
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}
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4 => {
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let value = LittleEndian::read_u32(data);
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match offset {
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0x0 => {
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self.msg_ctl = (self.msg_ctl & !(MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE))
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| ((value >> 16) as u16 & (MSI_CTL_ENABLE | MSI_CTL_MULTI_MSG_ENABLE))
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}
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MSI_MSG_ADDR_LO_OFFSET => self.msg_addr_lo = value & MSI_MSG_ADDR_LO_MASK,
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x if x == msg_data_offset => self.msg_data = value as u16,
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x if addr_hi_offset.is_some() && x == addr_hi_offset.unwrap() => {
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self.msg_addr_hi = value
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}
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x if mask_bits_offset.is_some() && x == mask_bits_offset.unwrap() => {
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self.mask_bits = value
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}
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_ => error!("invalid offset"),
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}
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}
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_ => error!("invalid data length"),
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}
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}
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}
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pub struct MsiConfig {
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cap: MsiCap,
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interrupt_source_group: Arc<Box<dyn InterruptSourceGroup>>,
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}
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impl MsiConfig {
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pub fn new(msg_ctl: u16, interrupt_source_group: Arc<Box<dyn InterruptSourceGroup>>) -> Self {
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let cap = MsiCap {
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msg_ctl,
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..Default::default()
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};
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MsiConfig {
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cap,
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interrupt_source_group,
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}
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}
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pub fn enabled(&self) -> bool {
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self.cap.enabled()
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}
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pub fn size(&self) -> u64 {
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self.cap.size()
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}
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pub fn num_enabled_vectors(&self) -> usize {
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self.cap.num_enabled_vectors()
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}
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pub fn update(&mut self, offset: u64, data: &[u8]) {
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let old_enabled = self.cap.enabled();
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self.cap.update(offset, data);
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if self.cap.enabled() {
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for idx in 0..self.num_enabled_vectors() {
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let config = MsiIrqSourceConfig {
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high_addr: self.cap.msg_addr_hi,
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low_addr: self.cap.msg_addr_lo,
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data: self.cap.msg_data as u32,
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devid: 0,
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};
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if let Err(e) = self
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.interrupt_source_group
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.update(idx as InterruptIndex, InterruptSourceConfig::MsiIrq(config))
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{
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error!("Failed updating vector: {:?}", e);
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}
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if self.cap.vector_masked(idx) {
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if let Err(e) = self.interrupt_source_group.mask(idx as InterruptIndex) {
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error!("Failed masking vector: {:?}", e);
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}
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} else if let Err(e) = self.interrupt_source_group.unmask(idx as InterruptIndex) {
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error!("Failed unmasking vector: {:?}", e);
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}
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}
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if !old_enabled {
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if let Err(e) = self.interrupt_source_group.enable() {
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error!("Failed enabling irq_fd: {:?}", e);
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}
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}
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} else if old_enabled {
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if let Err(e) = self.interrupt_source_group.disable() {
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error!("Failed disabling irq_fd: {:?}", e);
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}
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}
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}
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}
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