mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
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These are mostly due to use of "bare use" statements and unnecessary vector creation. Signed-off-by: Rob Bradford <robert.bradford@intel.com>
458 lines
14 KiB
Rust
458 lines
14 KiB
Rust
// Copyright 2018 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE-BSD-3-Clause file.
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use crate::configuration::{
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PciBarRegionType, PciBridgeSubclass, PciClassCode, PciConfiguration, PciHeaderType,
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};
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use crate::device::{DeviceRelocation, Error as PciDeviceError, PciDevice};
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use byteorder::{ByteOrder, LittleEndian};
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use devices::BusDevice;
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use std::any::Any;
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use std::collections::HashMap;
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use std::ops::DerefMut;
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use std::sync::{Arc, Mutex};
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use vm_memory::{Address, GuestAddress, GuestUsize};
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const VENDOR_ID_INTEL: u16 = 0x8086;
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const DEVICE_ID_INTEL_VIRT_PCIE_HOST: u16 = 0x0d57;
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const NUM_DEVICE_IDS: usize = 32;
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/// Errors for device manager.
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#[derive(Debug)]
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pub enum PciRootError {
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/// Could not allocate device address space for the device.
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AllocateDeviceAddrs(PciDeviceError),
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/// Could not allocate an IRQ number.
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AllocateIrq,
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/// Could not add a device to the port io bus.
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PioInsert(devices::BusError),
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/// Could not add a device to the mmio bus.
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MmioInsert(devices::BusError),
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/// Could not find an available device slot on the PCI bus.
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NoPciDeviceSlotAvailable,
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/// Invalid PCI device identifier provided.
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InvalidPciDeviceSlot(usize),
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/// Valid PCI device identifier but already used.
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AlreadyInUsePciDeviceSlot(usize),
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}
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pub type Result<T> = std::result::Result<T, PciRootError>;
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/// Emulates the PCI Root bridge device.
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pub struct PciRoot {
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/// Configuration space.
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config: PciConfiguration,
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}
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impl PciRoot {
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/// Create an empty PCI root bridge.
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pub fn new(config: Option<PciConfiguration>) -> Self {
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if let Some(config) = config {
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PciRoot { config }
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} else {
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PciRoot {
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config: PciConfiguration::new(
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VENDOR_ID_INTEL,
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DEVICE_ID_INTEL_VIRT_PCIE_HOST,
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0,
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PciClassCode::BridgeDevice,
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&PciBridgeSubclass::HostBridge,
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None,
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PciHeaderType::Device,
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0,
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0,
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None,
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),
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}
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}
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}
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}
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impl BusDevice for PciRoot {}
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impl PciDevice for PciRoot {
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fn write_config_register(&mut self, reg_idx: usize, offset: u64, data: &[u8]) {
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self.config.write_config_register(reg_idx, offset, data);
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}
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fn read_config_register(&mut self, reg_idx: usize) -> u32 {
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self.config.read_reg(reg_idx)
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}
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fn as_any(&mut self) -> &mut dyn Any {
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self
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}
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}
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pub struct PciBus {
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/// Devices attached to this bus.
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/// Device 0 is host bridge.
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devices: HashMap<u32, Arc<Mutex<dyn PciDevice>>>,
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device_reloc: Arc<dyn DeviceRelocation>,
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device_ids: Vec<bool>,
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}
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impl PciBus {
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pub fn new(pci_root: PciRoot, device_reloc: Arc<dyn DeviceRelocation>) -> Self {
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let mut devices: HashMap<u32, Arc<Mutex<dyn PciDevice>>> = HashMap::new();
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let mut device_ids: Vec<bool> = vec![false; NUM_DEVICE_IDS];
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devices.insert(0, Arc::new(Mutex::new(pci_root)));
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device_ids[0] = true;
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PciBus {
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devices,
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device_reloc,
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device_ids,
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}
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}
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pub fn register_mapping(
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&self,
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dev: Arc<Mutex<dyn BusDevice>>,
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io_bus: &devices::Bus,
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mmio_bus: &devices::Bus,
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bars: Vec<(GuestAddress, GuestUsize, PciBarRegionType)>,
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) -> Result<()> {
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for (address, size, type_) in bars {
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match type_ {
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PciBarRegionType::IORegion => {
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io_bus
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.insert(dev.clone(), address.raw_value(), size)
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.map_err(PciRootError::PioInsert)?;
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}
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PciBarRegionType::Memory32BitRegion | PciBarRegionType::Memory64BitRegion => {
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mmio_bus
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.insert(dev.clone(), address.raw_value(), size)
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.map_err(PciRootError::MmioInsert)?;
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}
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}
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}
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Ok(())
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}
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pub fn add_device(
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&mut self,
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pci_device_bdf: u32,
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device: Arc<Mutex<dyn PciDevice>>,
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) -> Result<()> {
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self.devices.insert(pci_device_bdf >> 3, device);
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Ok(())
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}
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pub fn remove_by_device(&mut self, device: &Arc<Mutex<dyn PciDevice>>) -> Result<()> {
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self.devices.retain(|_, dev| !Arc::ptr_eq(dev, device));
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Ok(())
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}
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pub fn next_device_id(&mut self) -> Result<u32> {
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for (idx, device_id) in self.device_ids.iter_mut().enumerate() {
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if !(*device_id) {
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*device_id = true;
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return Ok(idx as u32);
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}
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}
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Err(PciRootError::NoPciDeviceSlotAvailable)
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}
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pub fn get_device_id(&mut self, id: usize) -> Result<()> {
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if id < NUM_DEVICE_IDS {
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if !self.device_ids[id] {
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self.device_ids[id] = true;
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Ok(())
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} else {
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Err(PciRootError::AlreadyInUsePciDeviceSlot(id))
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}
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} else {
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Err(PciRootError::InvalidPciDeviceSlot(id))
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}
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}
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pub fn put_device_id(&mut self, id: usize) -> Result<()> {
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if id < NUM_DEVICE_IDS {
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self.device_ids[id] = false;
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Ok(())
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} else {
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Err(PciRootError::InvalidPciDeviceSlot(id))
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}
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}
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}
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pub struct PciConfigIo {
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/// Config space register.
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config_address: u32,
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pci_bus: Arc<Mutex<PciBus>>,
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}
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impl PciConfigIo {
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pub fn new(pci_bus: Arc<Mutex<PciBus>>) -> Self {
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PciConfigIo {
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pci_bus,
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config_address: 0,
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}
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}
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pub fn config_space_read(&self) -> u32 {
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let enabled = (self.config_address & 0x8000_0000) != 0;
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if !enabled {
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return 0xffff_ffff;
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}
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let (bus, device, function, register) =
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parse_io_config_address(self.config_address & !0x8000_0000);
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// Only support one bus.
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if bus != 0 {
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return 0xffff_ffff;
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}
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// Don't support multi-function devices.
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if function > 0 {
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return 0xffff_ffff;
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}
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self.pci_bus
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.lock()
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.unwrap()
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.devices
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.get(&(device as u32))
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.map_or(0xffff_ffff, |d| {
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d.lock().unwrap().read_config_register(register)
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})
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}
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pub fn config_space_write(&mut self, offset: u64, data: &[u8]) {
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if offset as usize + data.len() > 4 {
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return;
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}
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let enabled = (self.config_address & 0x8000_0000) != 0;
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if !enabled {
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return;
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}
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let (bus, device, _function, register) =
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parse_io_config_address(self.config_address & !0x8000_0000);
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// Only support one bus.
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if bus != 0 {
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return;
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}
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let pci_bus = self.pci_bus.lock().unwrap();
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if let Some(d) = pci_bus.devices.get(&(device as u32)) {
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let mut device = d.lock().unwrap();
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// Find out if one of the device's BAR is being reprogrammed, and
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// reprogram it if needed.
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if let Some(params) = device.detect_bar_reprogramming(register, data) {
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if let Err(e) = pci_bus.device_reloc.move_bar(
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params.old_base,
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params.new_base,
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params.len,
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device.deref_mut(),
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params.region_type,
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) {
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error!(
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"Failed moving device BAR: {}: 0x{:x}->0x{:x}(0x{:x})",
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e, params.old_base, params.new_base, params.len
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);
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}
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}
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// Update the register value
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device.write_config_register(register, offset, data);
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}
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}
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fn set_config_address(&mut self, offset: u64, data: &[u8]) {
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if offset as usize + data.len() > 4 {
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return;
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}
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let (mask, value): (u32, u32) = match data.len() {
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1 => (
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0x0000_00ff << (offset * 8),
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u32::from(data[0]) << (offset * 8),
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),
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2 => (
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0x0000_ffff << (offset * 16),
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(u32::from(data[1]) << 8 | u32::from(data[0])) << (offset * 16),
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),
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4 => (0xffff_ffff, LittleEndian::read_u32(data)),
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_ => return,
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};
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self.config_address = (self.config_address & !mask) | value;
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}
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}
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impl BusDevice for PciConfigIo {
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fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
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// `offset` is relative to 0xcf8
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let value = match offset {
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0..=3 => self.config_address,
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4..=7 => self.config_space_read(),
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_ => 0xffff_ffff,
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};
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// Only allow reads to the register boundary.
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let start = offset as usize % 4;
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let end = start + data.len();
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if end <= 4 {
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for i in start..end {
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data[i - start] = (value >> (i * 8)) as u8;
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}
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} else {
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for d in data {
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*d = 0xff;
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}
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}
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}
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fn write(&mut self, _base: u64, offset: u64, data: &[u8]) {
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// `offset` is relative to 0xcf8
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match offset {
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o @ 0..=3 => self.set_config_address(o, data),
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o @ 4..=7 => self.config_space_write(o - 4, data),
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_ => (),
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};
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}
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}
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/// Emulates PCI memory-mapped configuration access mechanism.
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pub struct PciConfigMmio {
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pci_bus: Arc<Mutex<PciBus>>,
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}
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impl PciConfigMmio {
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pub fn new(pci_bus: Arc<Mutex<PciBus>>) -> Self {
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PciConfigMmio { pci_bus }
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}
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fn config_space_read(&self, config_address: u32) -> u32 {
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let (bus, device, _function, register) = parse_mmio_config_address(config_address);
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// Only support one bus.
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if bus != 0 {
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return 0xffff_ffff;
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}
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self.pci_bus
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.lock()
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.unwrap()
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.devices
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.get(&(device as u32))
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.map_or(0xffff_ffff, |d| {
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d.lock().unwrap().read_config_register(register)
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})
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}
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fn config_space_write(&mut self, config_address: u32, offset: u64, data: &[u8]) {
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if offset as usize + data.len() > 4 {
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return;
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}
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let (bus, device, _function, register) = parse_mmio_config_address(config_address);
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// Only support one bus.
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if bus != 0 {
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return;
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}
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let pci_bus = self.pci_bus.lock().unwrap();
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if let Some(d) = pci_bus.devices.get(&(device as u32)) {
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let mut device = d.lock().unwrap();
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// Find out if one of the device's BAR is being reprogrammed, and
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// reprogram it if needed.
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if let Some(params) = device.detect_bar_reprogramming(register, data) {
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if let Err(e) = pci_bus.device_reloc.move_bar(
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params.old_base,
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params.new_base,
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params.len,
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device.deref_mut(),
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params.region_type,
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) {
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error!(
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"Failed moving device BAR: {}: 0x{:x}->0x{:x}(0x{:x})",
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e, params.old_base, params.new_base, params.len
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);
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}
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}
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// Update the register value
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device.write_config_register(register, offset, data);
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}
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}
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}
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impl BusDevice for PciConfigMmio {
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fn read(&mut self, _base: u64, offset: u64, data: &mut [u8]) {
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// Only allow reads to the register boundary.
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let start = offset as usize % 4;
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let end = start + data.len();
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if end > 4 || offset > u64::from(u32::max_value()) {
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for d in data {
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*d = 0xff;
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}
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return;
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}
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let value = self.config_space_read(offset as u32);
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for i in start..end {
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data[i - start] = (value >> (i * 8)) as u8;
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}
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}
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fn write(&mut self, _base: u64, offset: u64, data: &[u8]) {
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if offset > u64::from(u32::max_value()) {
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return;
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}
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self.config_space_write(offset as u32, offset % 4, data)
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}
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}
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fn shift_and_mask(value: u32, offset: usize, mask: u32) -> usize {
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((value >> offset) & mask) as usize
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}
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// Parse the MMIO address offset to a (bus, device, function, register) tuple.
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// See section 7.2.2 PCI Express Enhanced Configuration Access Mechanism (ECAM)
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// from the Pci Express Base Specification Revision 5.0 Version 1.0.
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fn parse_mmio_config_address(config_address: u32) -> (usize, usize, usize, usize) {
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const BUS_NUMBER_OFFSET: usize = 20;
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const BUS_NUMBER_MASK: u32 = 0x00ff;
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const DEVICE_NUMBER_OFFSET: usize = 15;
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const DEVICE_NUMBER_MASK: u32 = 0x1f;
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const FUNCTION_NUMBER_OFFSET: usize = 12;
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const FUNCTION_NUMBER_MASK: u32 = 0x07;
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const REGISTER_NUMBER_OFFSET: usize = 2;
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const REGISTER_NUMBER_MASK: u32 = 0x3ff;
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(
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shift_and_mask(config_address, BUS_NUMBER_OFFSET, BUS_NUMBER_MASK),
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shift_and_mask(config_address, DEVICE_NUMBER_OFFSET, DEVICE_NUMBER_MASK),
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shift_and_mask(config_address, FUNCTION_NUMBER_OFFSET, FUNCTION_NUMBER_MASK),
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shift_and_mask(config_address, REGISTER_NUMBER_OFFSET, REGISTER_NUMBER_MASK),
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)
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}
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// Parse the CONFIG_ADDRESS register to a (bus, device, function, register) tuple.
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fn parse_io_config_address(config_address: u32) -> (usize, usize, usize, usize) {
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const BUS_NUMBER_OFFSET: usize = 16;
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const BUS_NUMBER_MASK: u32 = 0x00ff;
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const DEVICE_NUMBER_OFFSET: usize = 11;
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const DEVICE_NUMBER_MASK: u32 = 0x1f;
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const FUNCTION_NUMBER_OFFSET: usize = 8;
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const FUNCTION_NUMBER_MASK: u32 = 0x07;
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const REGISTER_NUMBER_OFFSET: usize = 2;
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const REGISTER_NUMBER_MASK: u32 = 0x3f;
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(
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shift_and_mask(config_address, BUS_NUMBER_OFFSET, BUS_NUMBER_MASK),
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shift_and_mask(config_address, DEVICE_NUMBER_OFFSET, DEVICE_NUMBER_MASK),
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shift_and_mask(config_address, FUNCTION_NUMBER_OFFSET, FUNCTION_NUMBER_MASK),
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shift_and_mask(config_address, REGISTER_NUMBER_OFFSET, REGISTER_NUMBER_MASK),
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)
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}
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