mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
synced 2024-10-27 23:23:09 +00:00
0319a4a09a
Remove ACPI table creation from arch crate to the vmm crate simplifying arch::configure_system() GuestAddress(0) is used to mean no RSDP table rather than adding complexity with a conditional argument or an Option type as it will evaluate to a zero value which would be the default anyway. Signed-off-by: Rob Bradford <robert.bradford@intel.com>
454 lines
12 KiB
Rust
454 lines
12 KiB
Rust
// Copyright © 2019 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0
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//
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use acpi_tables::{
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aml,
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aml::Aml,
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rsdp::RSDP,
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sdt::{GenericAddress, SDT},
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};
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use vm_memory::{GuestAddress, GuestMemoryMmap};
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use vm_memory::{Address, ByteValued, Bytes};
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use std::convert::TryInto;
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use arch::layout;
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#[repr(packed)]
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struct LocalAPIC {
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pub r#type: u8,
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pub length: u8,
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pub processor_id: u8,
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pub apic_id: u8,
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pub flags: u32,
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}
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#[repr(packed)]
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#[derive(Default)]
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struct IOAPIC {
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pub r#type: u8,
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pub length: u8,
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pub ioapic_id: u8,
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_reserved: u8,
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pub apic_address: u32,
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pub gsi_base: u32,
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}
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#[repr(packed)]
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#[derive(Default)]
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struct InterruptSourceOverride {
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pub r#type: u8,
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pub length: u8,
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pub bus: u8,
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pub source: u8,
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pub gsi: u32,
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pub flags: u16,
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}
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#[repr(packed)]
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#[derive(Default)]
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struct PCIRangeEntry {
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pub base_address: u64,
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pub segment: u16,
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pub start: u8,
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pub end: u8,
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_reserved: u32,
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}
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#[repr(packed)]
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#[derive(Default)]
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struct IortParavirtIommuNode {
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pub type_: u8,
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pub length: u16,
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pub revision: u8,
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_reserved1: u32,
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pub num_id_mappings: u32,
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pub ref_id_mappings: u32,
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pub device_id: u32,
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_reserved2: [u32; 3],
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pub model: u32,
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pub flags: u32,
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_reserved3: [u32; 4],
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}
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#[repr(packed)]
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#[derive(Default)]
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struct IortPciRootComplexNode {
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pub type_: u8,
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pub length: u16,
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pub revision: u8,
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_reserved1: u32,
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pub num_id_mappings: u32,
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pub ref_id_mappings: u32,
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pub mem_access_props: IortMemoryAccessProperties,
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pub ats_attr: u32,
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pub pci_seg_num: u32,
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pub mem_addr_size_limit: u8,
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_reserved2: [u8; 3],
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}
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#[repr(packed)]
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#[derive(Default)]
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struct IortMemoryAccessProperties {
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pub cca: u32,
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pub ah: u8,
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_reserved: u16,
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pub maf: u8,
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}
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#[repr(packed)]
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#[derive(Default)]
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struct IortIdMapping {
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pub input_base: u32,
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pub num_of_ids: u32,
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pub ouput_base: u32,
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pub output_ref: u32,
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pub flags: u32,
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}
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struct CPU {
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cpu_id: u8,
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present: bool,
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}
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impl aml::Aml for CPU {
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fn to_aml_bytes(&self) -> Vec<u8> {
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aml::Device::new(
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format!("C{:03}", self.cpu_id).as_str().into(),
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vec![
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&aml::Name::new("_HID".into(), &"ACPI0007"),
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&aml::Name::new("_UID".into(), &self.cpu_id),
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/*
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_STA return value:
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Bit [0] – Set if the device is present.
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Bit [1] – Set if the device is enabled and decoding its resources.
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Bit [2] – Set if the device should be shown in the UI.
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Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics).
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Bit [4] – Set if the battery is present.
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Bits [31:5] – Reserved (must be cleared).
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*/
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&aml::Method::new(
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"_STA".into(),
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0,
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false,
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vec![&aml::Return::new(if self.present {
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&0xfu8
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} else {
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&aml::ZERO
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})],
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),
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],
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)
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.to_aml_bytes()
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}
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}
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fn create_cpu_data(num_cpus: u8) -> Vec<u8> {
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let hid = aml::Name::new("_HID".into(), &"ACPI0010");
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let uid = aml::Name::new("_CID".into(), &aml::EISAName::new("PNP0A05"));
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let mut cpu_data_inner: Vec<&dyn aml::Aml> = vec![&hid, &uid];
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let mut cpu_devices = Vec::new();
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for cpu_id in 0..num_cpus {
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let cpu_device = CPU {
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cpu_id,
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present: true,
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};
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cpu_devices.push(cpu_device);
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}
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for cpu_device in cpu_devices.iter() {
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cpu_data_inner.push(cpu_device);
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}
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aml::Device::new("_SB_.CPUS".into(), cpu_data_inner).to_aml_bytes()
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}
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pub fn create_dsdt_table(
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serial_enabled: bool,
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start_of_device_area: GuestAddress,
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end_of_device_area: GuestAddress,
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num_cpus: u8,
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) -> SDT {
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let pci_dsdt_data = aml::Device::new(
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"_SB_.PCI0".into(),
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vec![
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&aml::Name::new("_HID".into(), &aml::EISAName::new("PNP0A08")),
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&aml::Name::new("_CID".into(), &aml::EISAName::new("PNP0A03")),
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&aml::Name::new("_ADR".into(), &aml::ZERO),
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&aml::Name::new("_SEG".into(), &aml::ZERO),
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&aml::Name::new("_UID".into(), &aml::ZERO),
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&aml::Name::new("SUPP".into(), &aml::ZERO),
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&aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![
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&aml::AddressSpace::new_bus_number(0x0u16, 0xffu16),
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&aml::IO::new(0xcf8, 0xcf8, 1, 0x8),
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&aml::AddressSpace::new_io(0x0u16, 0xcf7u16),
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&aml::AddressSpace::new_io(0xd00u16, 0xffffu16),
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&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::NotCacheable,
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true,
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layout::MEM_32BIT_DEVICES_START.0 as u32,
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(layout::MEM_32BIT_DEVICES_START.0 + layout::MEM_32BIT_DEVICES_SIZE - 1)
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as u32,
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),
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&aml::AddressSpace::new_memory(
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aml::AddressSpaceCachable::NotCacheable,
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true,
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start_of_device_area.0,
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end_of_device_area.0,
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),
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]),
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),
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],
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)
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.to_aml_bytes();
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let mbrd_dsdt_data = aml::Device::new(
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"_SB_.MBRD".into(),
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vec![
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&aml::Name::new("_HID".into(), &aml::EISAName::new("PNP0C02")),
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&aml::Name::new("_UID".into(), &aml::ZERO),
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&aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![&aml::Memory32Fixed::new(
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true,
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layout::PCI_MMCONFIG_START.0 as u32,
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layout::PCI_MMCONFIG_SIZE as u32,
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)]),
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),
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],
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)
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.to_aml_bytes();
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let com1_dsdt_data = aml::Device::new(
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"_SB_.COM1".into(),
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vec![
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&aml::Name::new("_HID".into(), &aml::EISAName::new("PNP0501")),
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&aml::Name::new("_UID".into(), &aml::ZERO),
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&aml::Name::new(
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"_CRS".into(),
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&aml::ResourceTemplate::new(vec![
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&aml::Interrupt::new(true, true, false, false, 4),
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&aml::IO::new(0x3f8, 0x3f8, 0, 0x8),
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]),
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),
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],
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)
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.to_aml_bytes();
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let s5_sleep_data =
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aml::Name::new("_S5_".into(), &aml::Package::new(vec![&5u8])).to_aml_bytes();
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let cpu_data = create_cpu_data(num_cpus);
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// DSDT
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let mut dsdt = SDT::new(*b"DSDT", 36, 6, *b"CLOUDH", *b"CHDSDT ", 1);
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dsdt.append_slice(pci_dsdt_data.as_slice());
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dsdt.append_slice(mbrd_dsdt_data.as_slice());
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if serial_enabled {
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dsdt.append_slice(com1_dsdt_data.as_slice());
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}
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dsdt.append_slice(s5_sleep_data.as_slice());
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dsdt.append_slice(cpu_data.as_slice());
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dsdt
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}
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pub fn create_acpi_tables(
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guest_mem: &GuestMemoryMmap,
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num_cpus: u8,
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serial_enabled: bool,
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start_of_device_area: GuestAddress,
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end_of_device_area: GuestAddress,
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virt_iommu: Option<(u32, &[u32])>,
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) -> GuestAddress {
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// RSDP is at the EBDA
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let rsdp_offset = layout::RSDP_POINTER;
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let mut tables: Vec<u64> = Vec::new();
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// DSDT
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let dsdt = create_dsdt_table(
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serial_enabled,
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start_of_device_area,
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end_of_device_area,
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num_cpus,
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);
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let dsdt_offset = rsdp_offset.checked_add(RSDP::len() as u64).unwrap();
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guest_mem
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.write_slice(dsdt.as_slice(), dsdt_offset)
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.expect("Error writing DSDT table");
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// FACP aka FADT
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// Revision 6 of the ACPI FADT table is 276 bytes long
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let mut facp = SDT::new(*b"FACP", 276, 6, *b"CLOUDH", *b"CHFACP ", 1);
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// HW_REDUCED_ACPI and RESET_REG_SUP
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let fadt_flags: u32 = 1 << 20 | 1 << 10;
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facp.write(112, fadt_flags);
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// RESET_REG
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facp.write(116, GenericAddress::io_port_address(0x3c0));
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// RESET_VALUE
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facp.write(128, 1u8);
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facp.write(131, 3u8); // FADT minor version
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facp.write(140, dsdt_offset.0); // X_DSDT
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// SLEEP_CONTROL_REG
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facp.write(244, GenericAddress::io_port_address(0x3c0));
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// SLEEP_STATUS_REG
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facp.write(256, GenericAddress::io_port_address(0x3c0));
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facp.write(268, b"CLOUDHYP"); // Hypervisor Vendor Identity
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facp.update_checksum();
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let facp_offset = dsdt_offset.checked_add(dsdt.len() as u64).unwrap();
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guest_mem
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.write_slice(facp.as_slice(), facp_offset)
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.expect("Error writing FACP table");
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tables.push(facp_offset.0);
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// MADT
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let mut madt = SDT::new(*b"APIC", 44, 5, *b"CLOUDH", *b"CHMADT ", 1);
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madt.write(36, layout::APIC_START);
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for cpu in 0..num_cpus {
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let lapic = LocalAPIC {
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r#type: 0,
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length: 8,
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processor_id: cpu,
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apic_id: cpu,
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flags: 1,
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};
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madt.append(lapic);
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}
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madt.append(IOAPIC {
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r#type: 1,
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length: 12,
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ioapic_id: 0,
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apic_address: layout::IOAPIC_START.0 as u32,
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gsi_base: 0,
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..Default::default()
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});
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madt.append(InterruptSourceOverride {
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r#type: 2,
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length: 10,
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bus: 0,
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source: 4,
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gsi: 4,
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flags: 0,
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});
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let madt_offset = facp_offset.checked_add(facp.len() as u64).unwrap();
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guest_mem
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.write_slice(madt.as_slice(), madt_offset)
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.expect("Error writing MADT table");
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tables.push(madt_offset.0);
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// MCFG
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let mut mcfg = SDT::new(*b"MCFG", 36, 1, *b"CLOUDH", *b"CHMCFG ", 1);
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// MCFG reserved 8 bytes
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mcfg.append(0u64);
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// 32-bit PCI enhanced configuration mechanism
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mcfg.append(PCIRangeEntry {
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base_address: layout::PCI_MMCONFIG_START.0,
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segment: 0,
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start: 0,
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end: 0xff,
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..Default::default()
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});
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let mcfg_offset = madt_offset.checked_add(madt.len() as u64).unwrap();
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guest_mem
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.write_slice(mcfg.as_slice(), mcfg_offset)
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.expect("Error writing MCFG table");
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tables.push(mcfg_offset.0);
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let (prev_tbl_len, prev_tbl_off) = if let Some((iommu_id, dev_ids)) = &virt_iommu {
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// IORT
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let mut iort = SDT::new(*b"IORT", 36, 1, *b"CLOUDH", *b"CHIORT ", 1);
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// IORT number of nodes
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iort.append(2u32);
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// IORT offset to array of IORT nodes
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iort.append(48u32);
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// IORT reserved 4 bytes
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iort.append(0u32);
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// IORT paravirtualized IOMMU node
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iort.append(IortParavirtIommuNode {
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type_: 128,
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length: 56,
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revision: 0,
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num_id_mappings: 0,
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ref_id_mappings: 56,
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device_id: *iommu_id,
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model: 1,
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..Default::default()
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});
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let num_entries = dev_ids.len();
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let length: u16 = (36 + (20 * num_entries)).try_into().unwrap();
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// IORT PCI root complex node
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iort.append(IortPciRootComplexNode {
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type_: 2,
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length,
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revision: 0,
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num_id_mappings: num_entries as u32,
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ref_id_mappings: 36,
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ats_attr: 0,
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pci_seg_num: 0,
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mem_addr_size_limit: 255,
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..Default::default()
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});
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for dev_id in dev_ids.iter() {
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// IORT ID mapping
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iort.append(IortIdMapping {
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input_base: *dev_id,
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num_of_ids: 1,
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ouput_base: *dev_id,
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output_ref: 48,
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flags: 0,
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});
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}
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let iort_offset = mcfg_offset.checked_add(mcfg.len() as u64).unwrap();
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guest_mem
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.write_slice(iort.as_slice(), iort_offset)
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.expect("Error writing IORT table");
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tables.push(iort_offset.0);
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(iort.len(), iort_offset)
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} else {
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(mcfg.len(), mcfg_offset)
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};
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// XSDT
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let mut xsdt = SDT::new(*b"XSDT", 36, 1, *b"CLOUDH", *b"CHXSDT ", 1);
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for table in tables {
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xsdt.append(table);
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}
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xsdt.update_checksum();
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let xsdt_offset = prev_tbl_off.checked_add(prev_tbl_len as u64).unwrap();
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guest_mem
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.write_slice(xsdt.as_slice(), xsdt_offset)
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.expect("Error writing XSDT table");
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// RSDP
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let rsdp = RSDP::new(*b"CLOUDH", xsdt_offset.0);
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guest_mem
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.write_slice(rsdp.as_slice(), rsdp_offset)
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.expect("Error writing RSDP");
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rsdp_offset
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}
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