Rob Bradford a116add991 pci: configuration: Correctly mask MSI-X control register ... I incorrectly used the MSI message control register values for the mask not the the MSI-X control registers. The correct writable fields for MSI-X are only bits 14 and 15 of 2nd 16-bit word. Those are: * Function Mask: 14 * MSI-X Enable: 15 See "Table 7-47 Message Control Register for MSI-X" from "NCB-PCI_Express_Base_5.0r1.0-2019-05-22.pdf" Signed-off-by: Rob Bradford <robert.bradford@intel.com>		2022-02-22 16:33:49 +00:00
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src	pci: configuration: Correctly mask MSI-X control register	2022-02-22 16:33:49 +00:00
Cargo.toml	build: bump libc from 0.2.118 to 0.2.119	2022-02-22 09:55:13 +00:00