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ffaab46934
When a total ordering between multiple atomic variables is not required then use Ordering::Acquire with atomic loads and Ordering::Release with atomic stores. This will improve performance as this does not require a memory fence on x86_64 which Ordering::SeqCst will use. Add a comment to the code in the vCPU handling code where it operates on multiple atomics to explain why Ordering::SeqCst is required. Signed-off-by: Rob Bradford <robert.bradford@intel.com> |
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| .. | ||
| transport | ||
| vhost_user | ||
| vsock | ||
| balloon.rs | ||
| block_io_uring.rs | ||
| block.rs | ||
| console.rs | ||
| device.rs | ||
| epoll_helper.rs | ||
| iommu.rs | ||
| lib.rs | ||
| mem.rs | ||
| net_util.rs | ||
| net.rs | ||
| pmem.rs | ||
| rng.rs | ||
| seccomp_filters.rs | ||
| watchdog.rs | ||