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On AArch64, interrupt controller (GIC) is emulated by KVM. VMM need to set IRQ routing for devices, including legacy ones. Before this commit, IRQ routing was only set for MSI. Legacy routing entries of type KVM_IRQ_ROUTING_IRQCHIP were missing. That is way legacy devices (like serial device ttyS0) does not work. The setting of X86 IRQ routing entries are not impacted. Signed-off-by: Michael Zhao <michael.zhao@arm.com>
163 lines
5.9 KiB
Rust
163 lines
5.9 KiB
Rust
// Copyright 2018 The Chromium OS Authors. All rights reserved.
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// Copyright © 2019 Intel Corporation
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//
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// Portions Copyright 2017 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE-BSD-3-Clause file.
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//
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// SPDX-License-Identifier: Apache-2.0 AND BSD-3-Clause
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use vm_memory::{GuestAddress, GuestUsize};
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use crate::address::AddressAllocator;
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use crate::gsi::GsiAllocator;
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#[cfg(target_arch = "x86_64")]
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use crate::gsi::GsiApic;
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use libc::{sysconf, _SC_PAGESIZE};
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/// Safe wrapper for `sysconf(_SC_PAGESIZE)`.
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#[inline(always)]
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fn pagesize() -> usize {
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// Trivially safe
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unsafe { sysconf(_SC_PAGESIZE) as usize }
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}
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/// Manages allocating system resources such as address space and interrupt numbers.
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///
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/// # Example - Use the `SystemAddress` builder.
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///
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/// ```
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/// # #[cfg(target_arch = "x86_64")]
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/// # use vm_allocator::{GsiApic, SystemAllocator};
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/// # #[cfg(target_arch = "aarch64")]
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/// # use vm_allocator::SystemAllocator;
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/// # use vm_memory::{Address, GuestAddress, GuestUsize};
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/// let mut allocator = SystemAllocator::new(
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/// #[cfg(target_arch = "x86_64")] GuestAddress(0x1000),
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/// #[cfg(target_arch = "x86_64")] 0x10000,
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/// GuestAddress(0x10000000), 0x10000000,
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/// GuestAddress(0x20000000), 0x100000,
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/// #[cfg(target_arch = "x86_64")] vec![GsiApic::new(5, 19)]).unwrap();
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/// #[cfg(target_arch = "x86_64")]
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/// assert_eq!(allocator.allocate_irq(), Some(5));
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/// #[cfg(target_arch = "aarch64")]
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/// assert_eq!(allocator.allocate_irq(), Some(0));
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/// #[cfg(target_arch = "x86_64")]
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/// assert_eq!(allocator.allocate_irq(), Some(6));
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/// #[cfg(target_arch = "aarch64")]
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/// assert_eq!(allocator.allocate_irq(), Some(1));
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/// assert_eq!(allocator.allocate_mmio_addresses(None, 0x1000, Some(0x1000)), Some(GuestAddress(0x1fff_f000)));
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///
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/// ```
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pub struct SystemAllocator {
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#[cfg(target_arch = "x86_64")]
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io_address_space: AddressAllocator,
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mmio_address_space: AddressAllocator,
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mmio_hole_address_space: AddressAllocator,
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gsi_allocator: GsiAllocator,
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}
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impl SystemAllocator {
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/// Creates a new `SystemAllocator` for managing addresses and irq numvers.
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/// Can return `None` if `base` + `size` overflows a u64
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///
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/// * `io_base` - (X86) The starting address of IO memory.
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/// * `io_size` - (X86) The size of IO memory.
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/// * `mmio_base` - The starting address of MMIO memory.
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/// * `mmio_size` - The size of MMIO memory.
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/// * `mmio_hole_base` - The starting address of MMIO memory in 32-bit address space.
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/// * `mmio_hole_size` - The size of MMIO memory in 32-bit address space.
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/// * `apics` - (X86) Vector of APIC's.
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///
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pub fn new(
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#[cfg(target_arch = "x86_64")] io_base: GuestAddress,
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#[cfg(target_arch = "x86_64")] io_size: GuestUsize,
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mmio_base: GuestAddress,
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mmio_size: GuestUsize,
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mmio_hole_base: GuestAddress,
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mmio_hole_size: GuestUsize,
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#[cfg(target_arch = "x86_64")] apics: Vec<GsiApic>,
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) -> Option<Self> {
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Some(SystemAllocator {
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#[cfg(target_arch = "x86_64")]
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io_address_space: AddressAllocator::new(io_base, io_size)?,
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mmio_address_space: AddressAllocator::new(mmio_base, mmio_size)?,
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mmio_hole_address_space: AddressAllocator::new(mmio_hole_base, mmio_hole_size)?,
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#[cfg(target_arch = "x86_64")]
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gsi_allocator: GsiAllocator::new(apics),
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#[cfg(target_arch = "aarch64")]
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gsi_allocator: GsiAllocator::new(),
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})
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}
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/// Reserves the next available system irq number.
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pub fn allocate_irq(&mut self) -> Option<u32> {
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self.gsi_allocator.allocate_irq().ok()
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}
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/// Reserves the next available GSI.
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pub fn allocate_gsi(&mut self) -> Option<u32> {
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self.gsi_allocator.allocate_gsi().ok()
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}
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#[cfg(target_arch = "x86_64")]
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/// Reserves a section of `size` bytes of IO address space.
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pub fn allocate_io_addresses(
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&mut self,
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address: Option<GuestAddress>,
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size: GuestUsize,
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align_size: Option<GuestUsize>,
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) -> Option<GuestAddress> {
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self.io_address_space
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.allocate(address, size, Some(align_size.unwrap_or(0x1)))
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}
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/// Reserves a section of `size` bytes of MMIO address space.
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pub fn allocate_mmio_addresses(
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&mut self,
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address: Option<GuestAddress>,
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size: GuestUsize,
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align_size: Option<GuestUsize>,
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) -> Option<GuestAddress> {
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self.mmio_address_space.allocate(
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address,
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size,
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Some(align_size.unwrap_or(pagesize() as u64)),
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)
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}
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/// Reserves a section of `size` bytes of MMIO address space.
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pub fn allocate_mmio_hole_addresses(
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&mut self,
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address: Option<GuestAddress>,
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size: GuestUsize,
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align_size: Option<GuestUsize>,
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) -> Option<GuestAddress> {
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self.mmio_hole_address_space.allocate(
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address,
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size,
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Some(align_size.unwrap_or(pagesize() as u64)),
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)
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}
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#[cfg(target_arch = "x86_64")]
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/// Free an IO address range.
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/// We can only free a range if it matches exactly an already allocated range.
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pub fn free_io_addresses(&mut self, address: GuestAddress, size: GuestUsize) {
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self.io_address_space.free(address, size)
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}
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/// Free an MMIO address range.
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/// We can only free a range if it matches exactly an already allocated range.
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pub fn free_mmio_addresses(&mut self, address: GuestAddress, size: GuestUsize) {
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self.mmio_address_space.free(address, size)
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}
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/// Free an MMIO address range from the 32 bits hole.
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/// We can only free a range if it matches exactly an already allocated range.
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pub fn free_mmio_hole_addresses(&mut self, address: GuestAddress, size: GuestUsize) {
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self.mmio_hole_address_space.free(address, size)
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}
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}
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