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https://github.com/cloud-hypervisor/cloud-hypervisor.git
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9254b74c6d
Taking advantage of the refactored VFIO code implement a new VfioUserPciDevice that wraps the client for vfio-user and exposes the BusDevice and PciDevice into the VMM. Signed-off-by: Rob Bradford <robert.bradford@intel.com>
1288 lines
42 KiB
Rust
1288 lines
42 KiB
Rust
// Copyright © 2019 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0 OR BSD-3-Clause
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//
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use crate::{
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msi_num_enabled_vectors, BarReprogrammingParams, MsiConfig, MsixCap, MsixConfig,
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PciBarConfiguration, PciBarRegionType, PciCapabilityId, PciClassCode, PciConfiguration,
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PciDevice, PciDeviceError, PciHeaderType, PciSubclass, MSIX_TABLE_ENTRY_SIZE,
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};
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use byteorder::{ByteOrder, LittleEndian};
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use hypervisor::HypervisorVmError;
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use std::any::Any;
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use std::io;
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use std::os::unix::io::AsRawFd;
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use std::ptr::null_mut;
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use std::sync::{Arc, Barrier};
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use thiserror::Error;
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use vfio_bindings::bindings::vfio::*;
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use vfio_ioctls::{VfioContainer, VfioDevice, VfioIrq};
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use vm_allocator::SystemAllocator;
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use vm_device::interrupt::{
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InterruptIndex, InterruptManager, InterruptSourceGroup, MsiIrqGroupConfig,
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};
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use vm_device::BusDevice;
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use vm_memory::{Address, GuestAddress, GuestUsize};
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use vmm_sys_util::eventfd::EventFd;
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#[derive(Debug, Error)]
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pub enum VfioPciError {
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#[error("Failed to DMA map: {0}")]
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DmaMap(#[source] vfio_ioctls::VfioError),
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#[error("Failed to DMA unmap: {0}")]
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DmaUnmap(#[source] vfio_ioctls::VfioError),
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#[error("Failed to enable INTx: {0}")]
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EnableIntx(#[source] VfioError),
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#[error("Failed to enable MSI: {0}")]
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EnableMsi(#[source] VfioError),
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#[error("Failed to enable MSI-x: {0}")]
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EnableMsix(#[source] VfioError),
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#[error("Failed to map VFIO PCI region into guest: {0}")]
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MapRegionGuest(#[source] HypervisorVmError),
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#[error("Failed to notifier's eventfd")]
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MissingNotifier,
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}
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#[derive(Copy, Clone)]
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enum PciVfioSubclass {
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VfioSubclass = 0xff,
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}
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impl PciSubclass for PciVfioSubclass {
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fn get_register_value(&self) -> u8 {
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*self as u8
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}
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}
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enum InterruptUpdateAction {
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EnableMsi,
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DisableMsi,
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EnableMsix,
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DisableMsix,
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}
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pub(crate) struct VfioIntx {
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interrupt_source_group: Arc<dyn InterruptSourceGroup>,
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enabled: bool,
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}
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pub(crate) struct VfioMsi {
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pub(crate) cfg: MsiConfig,
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cap_offset: u32,
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interrupt_source_group: Arc<dyn InterruptSourceGroup>,
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}
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impl VfioMsi {
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fn update(&mut self, offset: u64, data: &[u8]) -> Option<InterruptUpdateAction> {
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let old_enabled = self.cfg.enabled();
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self.cfg.update(offset, data);
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let new_enabled = self.cfg.enabled();
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if !old_enabled && new_enabled {
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return Some(InterruptUpdateAction::EnableMsi);
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}
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if old_enabled && !new_enabled {
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return Some(InterruptUpdateAction::DisableMsi);
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}
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None
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}
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}
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pub(crate) struct VfioMsix {
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pub(crate) bar: MsixConfig,
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cap: MsixCap,
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cap_offset: u32,
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interrupt_source_group: Arc<dyn InterruptSourceGroup>,
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}
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impl VfioMsix {
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fn update(&mut self, offset: u64, data: &[u8]) -> Option<InterruptUpdateAction> {
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let old_enabled = self.bar.enabled();
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// Update "Message Control" word
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if offset == 2 && data.len() == 2 {
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self.bar.set_msg_ctl(LittleEndian::read_u16(data));
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}
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let new_enabled = self.bar.enabled();
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if !old_enabled && new_enabled {
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return Some(InterruptUpdateAction::EnableMsix);
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}
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if old_enabled && !new_enabled {
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return Some(InterruptUpdateAction::DisableMsix);
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}
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None
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}
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fn table_accessed(&self, bar_index: u32, offset: u64) -> bool {
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let table_offset: u64 = u64::from(self.cap.table_offset());
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let table_size: u64 = u64::from(self.cap.table_size()) * (MSIX_TABLE_ENTRY_SIZE as u64);
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let table_bir: u32 = self.cap.table_bir();
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bar_index == table_bir && offset >= table_offset && offset < table_offset + table_size
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}
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}
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pub(crate) struct Interrupt {
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pub(crate) intx: Option<VfioIntx>,
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pub(crate) msi: Option<VfioMsi>,
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pub(crate) msix: Option<VfioMsix>,
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}
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impl Interrupt {
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fn update_msi(&mut self, offset: u64, data: &[u8]) -> Option<InterruptUpdateAction> {
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if let Some(ref mut msi) = &mut self.msi {
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let action = msi.update(offset, data);
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return action;
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}
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None
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}
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fn update_msix(&mut self, offset: u64, data: &[u8]) -> Option<InterruptUpdateAction> {
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if let Some(ref mut msix) = &mut self.msix {
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let action = msix.update(offset, data);
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return action;
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}
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None
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}
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fn accessed(&self, offset: u64) -> Option<(PciCapabilityId, u64)> {
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if let Some(msi) = &self.msi {
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if offset >= u64::from(msi.cap_offset)
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&& offset < u64::from(msi.cap_offset) + msi.cfg.size()
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{
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return Some((
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PciCapabilityId::MessageSignalledInterrupts,
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u64::from(msi.cap_offset),
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));
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}
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}
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if let Some(msix) = &self.msix {
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if offset == u64::from(msix.cap_offset) {
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return Some((PciCapabilityId::MsiX, u64::from(msix.cap_offset)));
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}
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}
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None
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}
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fn msix_table_accessed(&self, bar_index: u32, offset: u64) -> bool {
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if let Some(msix) = &self.msix {
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return msix.table_accessed(bar_index, offset);
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}
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false
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}
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fn msix_write_table(&mut self, offset: u64, data: &[u8]) {
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if let Some(ref mut msix) = &mut self.msix {
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let offset = offset - u64::from(msix.cap.table_offset());
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msix.bar.write_table(offset, data)
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}
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}
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fn msix_read_table(&self, offset: u64, data: &mut [u8]) {
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if let Some(msix) = &self.msix {
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let offset = offset - u64::from(msix.cap.table_offset());
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msix.bar.read_table(offset, data)
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}
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}
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pub(crate) fn intx_in_use(&self) -> bool {
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if let Some(intx) = &self.intx {
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return intx.enabled;
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}
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false
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}
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}
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#[derive(Copy, Clone)]
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pub struct MmioRegion {
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pub start: GuestAddress,
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pub length: GuestUsize,
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pub(crate) type_: PciBarRegionType,
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pub(crate) index: u32,
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pub(crate) mem_slot: Option<u32>,
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pub(crate) host_addr: Option<u64>,
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pub(crate) mmap_size: Option<usize>,
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}
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#[derive(Debug, Error)]
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pub enum VfioError {
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#[error("Kernel VFIO error: {0}")]
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KernelVfio(#[source] vfio_ioctls::VfioError),
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#[error("VFIO user error: {0}")]
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VfioUser(#[source] vfio_user::Error),
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}
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pub(crate) trait Vfio {
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fn read_config_byte(&self, offset: u32) -> u8 {
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let mut data: [u8; 1] = [0];
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self.read_config(offset, &mut data);
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data[0]
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}
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fn read_config_word(&self, offset: u32) -> u16 {
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let mut data: [u8; 2] = [0, 0];
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self.read_config(offset, &mut data);
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u16::from_le_bytes(data)
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}
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fn read_config_dword(&self, offset: u32) -> u32 {
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let mut data: [u8; 4] = [0, 0, 0, 0];
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self.read_config(offset, &mut data);
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u32::from_le_bytes(data)
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}
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fn write_config_dword(&self, offset: u32, buf: u32) {
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let data: [u8; 4] = buf.to_le_bytes();
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self.write_config(offset, &data)
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}
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fn read_config(&self, offset: u32, data: &mut [u8]) {
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self.region_read(VFIO_PCI_CONFIG_REGION_INDEX, offset.into(), data.as_mut());
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}
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fn write_config(&self, offset: u32, data: &[u8]) {
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self.region_write(VFIO_PCI_CONFIG_REGION_INDEX, offset.into(), data)
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}
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fn enable_msi(&self, fds: Vec<&EventFd>) -> Result<(), VfioError> {
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self.enable_irq(VFIO_PCI_MSI_IRQ_INDEX, fds)
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}
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fn disable_msi(&self) -> Result<(), VfioError> {
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self.disable_irq(VFIO_PCI_MSI_IRQ_INDEX)
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}
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fn enable_msix(&self, fds: Vec<&EventFd>) -> Result<(), VfioError> {
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self.enable_irq(VFIO_PCI_MSIX_IRQ_INDEX, fds)
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}
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fn disable_msix(&self) -> Result<(), VfioError> {
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self.disable_irq(VFIO_PCI_MSIX_IRQ_INDEX)
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}
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fn region_read(&self, _index: u32, _offset: u64, _data: &mut [u8]) {
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unimplemented!()
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}
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fn region_write(&self, _index: u32, _offset: u64, _data: &[u8]) {
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unimplemented!()
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}
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fn get_irq_info(&self, _irq_index: u32) -> Option<VfioIrq> {
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unimplemented!()
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}
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fn enable_irq(&self, _irq_index: u32, _event_fds: Vec<&EventFd>) -> Result<(), VfioError> {
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unimplemented!()
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}
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fn disable_irq(&self, _irq_index: u32) -> Result<(), VfioError> {
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unimplemented!()
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}
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fn unmask_irq(&self, _irq_index: u32) -> Result<(), VfioError> {
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unimplemented!()
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}
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}
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struct VfioDeviceWrapper {
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device: Arc<VfioDevice>,
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}
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impl VfioDeviceWrapper {
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fn new(device: Arc<VfioDevice>) -> Self {
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Self { device }
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}
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}
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impl Vfio for VfioDeviceWrapper {
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fn region_read(&self, index: u32, offset: u64, data: &mut [u8]) {
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self.device.region_read(index, data, offset)
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}
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fn region_write(&self, index: u32, offset: u64, data: &[u8]) {
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self.device.region_write(index, data, offset)
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}
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fn get_irq_info(&self, irq_index: u32) -> Option<VfioIrq> {
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self.device.get_irq_info(irq_index).copied()
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}
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fn enable_irq(&self, irq_index: u32, event_fds: Vec<&EventFd>) -> Result<(), VfioError> {
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self.device
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.enable_irq(irq_index, event_fds)
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.map_err(VfioError::KernelVfio)
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}
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fn disable_irq(&self, irq_index: u32) -> Result<(), VfioError> {
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self.device
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.disable_irq(irq_index)
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.map_err(VfioError::KernelVfio)
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}
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fn unmask_irq(&self, irq_index: u32) -> Result<(), VfioError> {
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self.device
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.unmask_irq(irq_index)
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.map_err(VfioError::KernelVfio)
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}
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}
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pub(crate) struct VfioCommon {
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pub(crate) configuration: PciConfiguration,
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pub(crate) mmio_regions: Vec<MmioRegion>,
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pub(crate) interrupt: Interrupt,
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}
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impl VfioCommon {
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pub(crate) fn allocate_bars(
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&mut self,
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allocator: &mut SystemAllocator,
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vfio_wrapper: &dyn Vfio,
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) -> Result<Vec<(GuestAddress, GuestUsize, PciBarRegionType)>, PciDeviceError> {
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let mut ranges = Vec::new();
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let mut bar_id = VFIO_PCI_BAR0_REGION_INDEX as u32;
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// Going through all regular regions to compute the BAR size.
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// We're not saving the BAR address to restore it, because we
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// are going to allocate a guest address for each BAR and write
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// that new address back.
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while bar_id < VFIO_PCI_CONFIG_REGION_INDEX {
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let region_size: u64;
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let bar_addr: GuestAddress;
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let bar_offset = if bar_id == VFIO_PCI_ROM_REGION_INDEX {
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(PCI_ROM_EXP_BAR_INDEX * 4) as u32
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} else {
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PCI_CONFIG_BAR_OFFSET + bar_id * 4
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};
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// First read flags
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let flags = vfio_wrapper.read_config_dword(bar_offset);
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// Is this an IO BAR?
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let io_bar = if bar_id != VFIO_PCI_ROM_REGION_INDEX {
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matches!(flags & PCI_CONFIG_IO_BAR, PCI_CONFIG_IO_BAR)
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} else {
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false
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};
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// Is this a 64-bit BAR?
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let is_64bit_bar = if bar_id != VFIO_PCI_ROM_REGION_INDEX {
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matches!(
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flags & PCI_CONFIG_MEMORY_BAR_64BIT,
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PCI_CONFIG_MEMORY_BAR_64BIT
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)
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} else {
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false
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};
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// By default, the region type is 32 bits memory BAR.
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let mut region_type = PciBarRegionType::Memory32BitRegion;
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// To get size write all 1s
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vfio_wrapper.write_config_dword(bar_offset, 0xffff_ffff);
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// And read back BAR value. The device will write zeros for bits it doesn't care about
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let mut lower = vfio_wrapper.read_config_dword(bar_offset);
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if io_bar {
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#[cfg(target_arch = "x86_64")]
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{
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// IO BAR
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region_type = PciBarRegionType::IoRegion;
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// Mask flag bits (lowest 2 for I/O bars)
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lower &= !0b11;
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// BAR is not enabled
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if lower == 0 {
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bar_id += 1;
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continue;
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}
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// Invert bits and add 1 to calculate size
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region_size = (!lower + 1) as u64;
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// The address needs to be 4 bytes aligned.
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bar_addr = allocator
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.allocate_io_addresses(None, region_size, Some(0x4))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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}
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#[cfg(target_arch = "aarch64")]
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unimplemented!()
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} else if is_64bit_bar {
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// 64 bits Memory BAR
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region_type = PciBarRegionType::Memory64BitRegion;
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// Query size of upper BAR of 64-bit BAR
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let upper_offset: u32 = PCI_CONFIG_BAR_OFFSET + (bar_id + 1) * 4;
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vfio_wrapper.write_config_dword(upper_offset, 0xffff_ffff);
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let upper = vfio_wrapper.read_config_dword(upper_offset);
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let mut combined_size = u64::from(upper) << 32 | u64::from(lower);
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// Mask out flag bits (lowest 4 for memory bars)
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combined_size &= !0b1111;
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// BAR is not enabled
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if combined_size == 0 {
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bar_id += 1;
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continue;
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}
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// Invert and add 1 to to find size
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region_size = (!combined_size + 1) as u64;
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// BAR allocation must be naturally aligned
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bar_addr = allocator
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.allocate_mmio_addresses(None, region_size, Some(region_size))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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} else {
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// Mask out flag bits (lowest 4 for memory bars)
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lower &= !0b1111;
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if lower == 0 {
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bar_id += 1;
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continue;
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}
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// Invert and add 1 to to find size
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region_size = (!lower + 1) as u64;
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// BAR allocation must be naturally aligned
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bar_addr = allocator
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.allocate_mmio_hole_addresses(None, region_size, Some(region_size))
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.ok_or(PciDeviceError::IoAllocationFailed(region_size))?;
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}
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let reg_idx = if bar_id == VFIO_PCI_ROM_REGION_INDEX {
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PCI_ROM_EXP_BAR_INDEX
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} else {
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bar_id as usize
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};
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// We can now build our BAR configuration block.
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let config = PciBarConfiguration::default()
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.set_register_index(reg_idx)
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.set_address(bar_addr.raw_value())
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.set_size(region_size)
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.set_region_type(region_type);
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if bar_id == VFIO_PCI_ROM_REGION_INDEX {
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self.configuration
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.add_pci_rom_bar(&config, flags & 0x1)
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.map_err(|e| PciDeviceError::IoRegistrationFailed(bar_addr.raw_value(), e))?;
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} else {
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self.configuration
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.add_pci_bar(&config)
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.map_err(|e| PciDeviceError::IoRegistrationFailed(bar_addr.raw_value(), e))?;
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}
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|
|
ranges.push((bar_addr, region_size, region_type));
|
|
self.mmio_regions.push(MmioRegion {
|
|
start: bar_addr,
|
|
length: region_size,
|
|
type_: region_type,
|
|
index: bar_id as u32,
|
|
mem_slot: None,
|
|
host_addr: None,
|
|
mmap_size: None,
|
|
});
|
|
|
|
bar_id += 1;
|
|
if is_64bit_bar {
|
|
bar_id += 1;
|
|
}
|
|
}
|
|
|
|
Ok(ranges)
|
|
}
|
|
|
|
pub(crate) fn free_bars(
|
|
&mut self,
|
|
allocator: &mut SystemAllocator,
|
|
) -> Result<(), PciDeviceError> {
|
|
for region in self.mmio_regions.iter() {
|
|
match region.type_ {
|
|
PciBarRegionType::IoRegion => {
|
|
#[cfg(target_arch = "x86_64")]
|
|
allocator.free_io_addresses(region.start, region.length);
|
|
#[cfg(target_arch = "aarch64")]
|
|
error!("I/O region is not supported");
|
|
}
|
|
PciBarRegionType::Memory32BitRegion => {
|
|
allocator.free_mmio_hole_addresses(region.start, region.length);
|
|
}
|
|
PciBarRegionType::Memory64BitRegion => {
|
|
allocator.free_mmio_addresses(region.start, region.length);
|
|
}
|
|
}
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
pub(crate) fn parse_msix_capabilities(
|
|
&mut self,
|
|
cap: u8,
|
|
interrupt_manager: &Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
|
|
vfio_wrapper: &dyn Vfio,
|
|
) {
|
|
let msg_ctl = vfio_wrapper.read_config_word((cap + 2).into());
|
|
|
|
let table = vfio_wrapper.read_config_dword((cap + 4).into());
|
|
|
|
let pba = vfio_wrapper.read_config_dword((cap + 8).into());
|
|
|
|
let msix_cap = MsixCap {
|
|
msg_ctl,
|
|
table,
|
|
pba,
|
|
};
|
|
|
|
let interrupt_source_group = interrupt_manager
|
|
.create_group(MsiIrqGroupConfig {
|
|
base: 0,
|
|
count: msix_cap.table_size() as InterruptIndex,
|
|
})
|
|
.unwrap();
|
|
|
|
let msix_config = MsixConfig::new(msix_cap.table_size(), interrupt_source_group.clone(), 0);
|
|
|
|
self.interrupt.msix = Some(VfioMsix {
|
|
bar: msix_config,
|
|
cap: msix_cap,
|
|
cap_offset: cap.into(),
|
|
interrupt_source_group,
|
|
});
|
|
}
|
|
|
|
pub(crate) fn parse_msi_capabilities(
|
|
&mut self,
|
|
cap: u8,
|
|
interrupt_manager: &Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
|
|
vfio_wrapper: &dyn Vfio,
|
|
) {
|
|
let msg_ctl = vfio_wrapper.read_config_word((cap + 2).into());
|
|
|
|
let interrupt_source_group = interrupt_manager
|
|
.create_group(MsiIrqGroupConfig {
|
|
base: 0,
|
|
count: msi_num_enabled_vectors(msg_ctl) as InterruptIndex,
|
|
})
|
|
.unwrap();
|
|
|
|
let msi_config = MsiConfig::new(msg_ctl, interrupt_source_group.clone());
|
|
|
|
self.interrupt.msi = Some(VfioMsi {
|
|
cfg: msi_config,
|
|
cap_offset: cap.into(),
|
|
interrupt_source_group,
|
|
});
|
|
}
|
|
|
|
pub(crate) fn parse_capabilities(
|
|
&mut self,
|
|
interrupt_manager: &Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
|
|
vfio_wrapper: &dyn Vfio,
|
|
) {
|
|
let mut cap_next = vfio_wrapper.read_config_byte(PCI_CONFIG_CAPABILITY_OFFSET);
|
|
|
|
while cap_next != 0 {
|
|
let cap_id = vfio_wrapper.read_config_byte(cap_next.into());
|
|
|
|
match PciCapabilityId::from(cap_id) {
|
|
PciCapabilityId::MessageSignalledInterrupts => {
|
|
if let Some(irq_info) = vfio_wrapper.get_irq_info(VFIO_PCI_MSI_IRQ_INDEX) {
|
|
if irq_info.count > 0 {
|
|
// Parse capability only if the VFIO device
|
|
// supports MSI.
|
|
self.parse_msi_capabilities(cap_next, interrupt_manager, vfio_wrapper);
|
|
}
|
|
}
|
|
}
|
|
PciCapabilityId::MsiX => {
|
|
if let Some(irq_info) = vfio_wrapper.get_irq_info(VFIO_PCI_MSIX_IRQ_INDEX) {
|
|
if irq_info.count > 0 {
|
|
// Parse capability only if the VFIO device
|
|
// supports MSI-X.
|
|
self.parse_msix_capabilities(cap_next, interrupt_manager, vfio_wrapper);
|
|
}
|
|
}
|
|
}
|
|
_ => {}
|
|
};
|
|
|
|
cap_next = vfio_wrapper.read_config_byte((cap_next + 1).into());
|
|
}
|
|
}
|
|
|
|
pub(crate) fn enable_intx(&mut self, wrapper: &dyn Vfio) -> Result<(), VfioPciError> {
|
|
if let Some(intx) = &mut self.interrupt.intx {
|
|
if !intx.enabled {
|
|
if let Some(eventfd) = intx.interrupt_source_group.notifier(0) {
|
|
wrapper
|
|
.enable_irq(VFIO_PCI_INTX_IRQ_INDEX, vec![&eventfd])
|
|
.map_err(VfioPciError::EnableIntx)?;
|
|
|
|
intx.enabled = true;
|
|
} else {
|
|
return Err(VfioPciError::MissingNotifier);
|
|
}
|
|
}
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
pub(crate) fn disable_intx(&mut self, wrapper: &dyn Vfio) {
|
|
if let Some(intx) = &mut self.interrupt.intx {
|
|
if intx.enabled {
|
|
if let Err(e) = wrapper.disable_irq(VFIO_PCI_INTX_IRQ_INDEX) {
|
|
error!("Could not disable INTx: {}", e);
|
|
} else {
|
|
intx.enabled = false;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
pub(crate) fn enable_msi(&self, wrapper: &dyn Vfio) -> Result<(), VfioPciError> {
|
|
if let Some(msi) = &self.interrupt.msi {
|
|
let mut irq_fds: Vec<EventFd> = Vec::new();
|
|
for i in 0..msi.cfg.num_enabled_vectors() {
|
|
if let Some(eventfd) = msi.interrupt_source_group.notifier(i as InterruptIndex) {
|
|
irq_fds.push(eventfd);
|
|
} else {
|
|
return Err(VfioPciError::MissingNotifier);
|
|
}
|
|
}
|
|
|
|
wrapper
|
|
.enable_msi(irq_fds.iter().collect())
|
|
.map_err(VfioPciError::EnableMsi)?;
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
pub(crate) fn disable_msi(&self, wrapper: &dyn Vfio) {
|
|
if let Err(e) = wrapper.disable_msi() {
|
|
error!("Could not disable MSI: {}", e);
|
|
}
|
|
}
|
|
|
|
pub(crate) fn enable_msix(&self, wrapper: &dyn Vfio) -> Result<(), VfioPciError> {
|
|
if let Some(msix) = &self.interrupt.msix {
|
|
let mut irq_fds: Vec<EventFd> = Vec::new();
|
|
for i in 0..msix.bar.table_entries.len() {
|
|
if let Some(eventfd) = msix.interrupt_source_group.notifier(i as InterruptIndex) {
|
|
irq_fds.push(eventfd);
|
|
} else {
|
|
return Err(VfioPciError::MissingNotifier);
|
|
}
|
|
}
|
|
|
|
wrapper
|
|
.enable_msix(irq_fds.iter().collect())
|
|
.map_err(VfioPciError::EnableMsix)?;
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
pub(crate) fn disable_msix(&self, wrapper: &dyn Vfio) {
|
|
if let Err(e) = wrapper.disable_msix() {
|
|
error!("Could not disable MSI-X: {}", e);
|
|
}
|
|
}
|
|
|
|
pub(crate) fn initialize_legacy_interrupt(
|
|
&mut self,
|
|
legacy_interrupt_group: Option<Arc<dyn InterruptSourceGroup>>,
|
|
wrapper: &dyn Vfio,
|
|
) -> Result<(), VfioPciError> {
|
|
if let Some(irq_info) = wrapper.get_irq_info(VFIO_PCI_INTX_IRQ_INDEX) {
|
|
if irq_info.count == 0 {
|
|
// A count of 0 means the INTx IRQ is not supported, therefore
|
|
// it shouldn't be initialized.
|
|
return Ok(());
|
|
}
|
|
}
|
|
|
|
if let Some(interrupt_source_group) = legacy_interrupt_group {
|
|
self.interrupt.intx = Some(VfioIntx {
|
|
interrupt_source_group,
|
|
enabled: false,
|
|
});
|
|
|
|
self.enable_intx(wrapper)?;
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
pub(crate) fn update_msi_capabilities(
|
|
&mut self,
|
|
offset: u64,
|
|
data: &[u8],
|
|
wrapper: &dyn Vfio,
|
|
) -> Result<(), VfioPciError> {
|
|
match self.interrupt.update_msi(offset, data) {
|
|
Some(InterruptUpdateAction::EnableMsi) => {
|
|
// Disable INTx before we can enable MSI
|
|
self.disable_intx(wrapper);
|
|
self.enable_msi(wrapper)?;
|
|
}
|
|
Some(InterruptUpdateAction::DisableMsi) => {
|
|
// Fallback onto INTx when disabling MSI
|
|
self.disable_msi(wrapper);
|
|
self.enable_intx(wrapper)?;
|
|
}
|
|
_ => {}
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
pub(crate) fn update_msix_capabilities(
|
|
&mut self,
|
|
offset: u64,
|
|
data: &[u8],
|
|
wrapper: &dyn Vfio,
|
|
) -> Result<(), VfioPciError> {
|
|
match self.interrupt.update_msix(offset, data) {
|
|
Some(InterruptUpdateAction::EnableMsix) => {
|
|
// Disable INTx before we can enable MSI-X
|
|
self.disable_intx(wrapper);
|
|
self.enable_msix(wrapper)?;
|
|
}
|
|
Some(InterruptUpdateAction::DisableMsix) => {
|
|
// Fallback onto INTx when disabling MSI-X
|
|
self.disable_msix(wrapper);
|
|
self.enable_intx(wrapper)?;
|
|
}
|
|
_ => {}
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
pub(crate) fn find_region(&self, addr: u64) -> Option<MmioRegion> {
|
|
for region in self.mmio_regions.iter() {
|
|
if addr >= region.start.raw_value()
|
|
&& addr < region.start.unchecked_add(region.length).raw_value()
|
|
{
|
|
return Some(*region);
|
|
}
|
|
}
|
|
None
|
|
}
|
|
|
|
pub(crate) fn read_bar(&mut self, base: u64, offset: u64, data: &mut [u8], wrapper: &dyn Vfio) {
|
|
let addr = base + offset;
|
|
if let Some(region) = self.find_region(addr) {
|
|
let offset = addr - region.start.raw_value();
|
|
|
|
if self.interrupt.msix_table_accessed(region.index, offset) {
|
|
self.interrupt.msix_read_table(offset, data);
|
|
} else {
|
|
wrapper.region_read(region.index, offset, data);
|
|
}
|
|
}
|
|
|
|
// INTx EOI
|
|
// The guest reading from the BAR potentially means the interrupt has
|
|
// been received and can be acknowledged.
|
|
if self.interrupt.intx_in_use() {
|
|
if let Err(e) = wrapper.unmask_irq(VFIO_PCI_INTX_IRQ_INDEX) {
|
|
error!("Failed unmasking INTx IRQ: {}", e);
|
|
}
|
|
}
|
|
}
|
|
|
|
pub(crate) fn write_bar(
|
|
&mut self,
|
|
base: u64,
|
|
offset: u64,
|
|
data: &[u8],
|
|
wrapper: &dyn Vfio,
|
|
) -> Option<Arc<Barrier>> {
|
|
let addr = base + offset;
|
|
if let Some(region) = self.find_region(addr) {
|
|
let offset = addr - region.start.raw_value();
|
|
|
|
// If the MSI-X table is written to, we need to update our cache.
|
|
if self.interrupt.msix_table_accessed(region.index, offset) {
|
|
self.interrupt.msix_write_table(offset, data);
|
|
} else {
|
|
wrapper.region_write(region.index, offset, data);
|
|
}
|
|
}
|
|
|
|
// INTx EOI
|
|
// The guest writing to the BAR potentially means the interrupt has
|
|
// been received and can be acknowledged.
|
|
if self.interrupt.intx_in_use() {
|
|
if let Err(e) = wrapper.unmask_irq(VFIO_PCI_INTX_IRQ_INDEX) {
|
|
error!("Failed unmasking INTx IRQ: {}", e);
|
|
}
|
|
}
|
|
|
|
None
|
|
}
|
|
|
|
pub(crate) fn write_config_register(
|
|
&mut self,
|
|
reg_idx: usize,
|
|
offset: u64,
|
|
data: &[u8],
|
|
wrapper: &dyn Vfio,
|
|
) -> Option<Arc<Barrier>> {
|
|
// When the guest wants to write to a BAR, we trap it into
|
|
// our local configuration space. We're not reprogramming
|
|
// VFIO device.
|
|
if (PCI_CONFIG_BAR0_INDEX..PCI_CONFIG_BAR0_INDEX + BAR_NUMS).contains(®_idx)
|
|
|| reg_idx == PCI_ROM_EXP_BAR_INDEX
|
|
{
|
|
// We keep our local cache updated with the BARs.
|
|
// We'll read it back from there when the guest is asking
|
|
// for BARs (see read_config_register()).
|
|
self.configuration
|
|
.write_config_register(reg_idx, offset, data);
|
|
return None;
|
|
}
|
|
|
|
let reg = (reg_idx * PCI_CONFIG_REGISTER_SIZE) as u64;
|
|
|
|
// If the MSI or MSI-X capabilities are accessed, we need to
|
|
// update our local cache accordingly.
|
|
// Depending on how the capabilities are modified, this could
|
|
// trigger a VFIO MSI or MSI-X toggle.
|
|
if let Some((cap_id, cap_base)) = self.interrupt.accessed(reg) {
|
|
let cap_offset: u64 = reg - cap_base + offset;
|
|
match cap_id {
|
|
PciCapabilityId::MessageSignalledInterrupts => {
|
|
if let Err(e) = self.update_msi_capabilities(cap_offset, data, wrapper) {
|
|
error!("Could not update MSI capabilities: {}", e);
|
|
}
|
|
}
|
|
PciCapabilityId::MsiX => {
|
|
if let Err(e) = self.update_msix_capabilities(cap_offset, data, wrapper) {
|
|
error!("Could not update MSI-X capabilities: {}", e);
|
|
}
|
|
}
|
|
_ => {}
|
|
}
|
|
}
|
|
|
|
// Make sure to write to the device's PCI config space after MSI/MSI-X
|
|
// interrupts have been enabled/disabled. In case of MSI, when the
|
|
// interrupts are enabled through VFIO (using VFIO_DEVICE_SET_IRQS),
|
|
// the MSI Enable bit in the MSI capability structure found in the PCI
|
|
// config space is disabled by default. That's why when the guest is
|
|
// enabling this bit, we first need to enable the MSI interrupts with
|
|
// VFIO through VFIO_DEVICE_SET_IRQS ioctl, and only after we can write
|
|
// to the device region to update the MSI Enable bit.
|
|
wrapper.write_config((reg + offset) as u32, data);
|
|
|
|
None
|
|
}
|
|
|
|
pub(crate) fn read_config_register(&mut self, reg_idx: usize, wrapper: &dyn Vfio) -> u32 {
|
|
// When reading the BARs, we trap it and return what comes
|
|
// from our local configuration space. We want the guest to
|
|
// use that and not the VFIO device BARs as it does not map
|
|
// with the guest address space.
|
|
if (PCI_CONFIG_BAR0_INDEX..PCI_CONFIG_BAR0_INDEX + BAR_NUMS).contains(®_idx)
|
|
|| reg_idx == PCI_ROM_EXP_BAR_INDEX
|
|
{
|
|
return self.configuration.read_reg(reg_idx);
|
|
}
|
|
|
|
// Since we don't support passing multi-functions devices, we should
|
|
// mask the multi-function bit, bit 7 of the Header Type byte on the
|
|
// register 3.
|
|
let mask = if reg_idx == PCI_HEADER_TYPE_REG_INDEX {
|
|
0xff7f_ffff
|
|
} else {
|
|
0xffff_ffff
|
|
};
|
|
|
|
// The config register read comes from the VFIO device itself.
|
|
wrapper.read_config_dword((reg_idx * 4) as u32) & mask
|
|
}
|
|
}
|
|
|
|
/// VfioPciDevice represents a VFIO PCI device.
|
|
/// This structure implements the BusDevice and PciDevice traits.
|
|
///
|
|
/// A VfioPciDevice is bound to a VfioDevice and is also a PCI device.
|
|
/// The VMM creates a VfioDevice, then assigns it to a VfioPciDevice,
|
|
/// which then gets added to the PCI bus.
|
|
pub struct VfioPciDevice {
|
|
vm: Arc<dyn hypervisor::Vm>,
|
|
device: Arc<VfioDevice>,
|
|
container: Arc<VfioContainer>,
|
|
vfio_wrapper: VfioDeviceWrapper,
|
|
common: VfioCommon,
|
|
iommu_attached: bool,
|
|
}
|
|
|
|
impl VfioPciDevice {
|
|
/// Constructs a new Vfio Pci device for the given Vfio device
|
|
pub fn new(
|
|
vm: &Arc<dyn hypervisor::Vm>,
|
|
device: VfioDevice,
|
|
container: Arc<VfioContainer>,
|
|
msi_interrupt_manager: &Arc<dyn InterruptManager<GroupConfig = MsiIrqGroupConfig>>,
|
|
legacy_interrupt_group: Option<Arc<dyn InterruptSourceGroup>>,
|
|
iommu_attached: bool,
|
|
) -> Result<Self, VfioPciError> {
|
|
let device = Arc::new(device);
|
|
device.reset();
|
|
|
|
let configuration = PciConfiguration::new(
|
|
0,
|
|
0,
|
|
0,
|
|
PciClassCode::Other,
|
|
&PciVfioSubclass::VfioSubclass,
|
|
None,
|
|
PciHeaderType::Device,
|
|
0,
|
|
0,
|
|
None,
|
|
);
|
|
|
|
let vfio_wrapper = VfioDeviceWrapper::new(Arc::clone(&device));
|
|
|
|
let mut common = VfioCommon {
|
|
mmio_regions: Vec::new(),
|
|
configuration,
|
|
interrupt: Interrupt {
|
|
intx: None,
|
|
msi: None,
|
|
msix: None,
|
|
},
|
|
};
|
|
|
|
common.parse_capabilities(msi_interrupt_manager, &vfio_wrapper);
|
|
common.initialize_legacy_interrupt(legacy_interrupt_group, &vfio_wrapper)?;
|
|
|
|
let vfio_pci_device = VfioPciDevice {
|
|
vm: vm.clone(),
|
|
device,
|
|
container,
|
|
vfio_wrapper,
|
|
common,
|
|
iommu_attached,
|
|
};
|
|
|
|
Ok(vfio_pci_device)
|
|
}
|
|
|
|
pub fn iommu_attached(&self) -> bool {
|
|
self.iommu_attached
|
|
}
|
|
|
|
/// Map MMIO regions into the guest, and avoid VM exits when the guest tries
|
|
/// to reach those regions.
|
|
///
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/// # Arguments
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///
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/// * `vm` - The VM object. It is used to set the VFIO MMIO regions
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/// as user memory regions.
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/// * `mem_slot` - The closure to return a memory slot.
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pub fn map_mmio_regions<F>(
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&mut self,
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vm: &Arc<dyn hypervisor::Vm>,
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mem_slot: F,
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) -> Result<(), VfioPciError>
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where
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F: Fn() -> u32,
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{
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let fd = self.device.as_raw_fd();
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for region in self.common.mmio_regions.iter_mut() {
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// We want to skip the mapping of the BAR containing the MSI-X
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// table even if it is mappable. The reason is we need to trap
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// any access to the MSI-X table and update the GSI routing
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// accordingly.
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if let Some(msix) = &self.common.interrupt.msix {
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if region.index == msix.cap.table_bir() || region.index == msix.cap.pba_bir() {
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continue;
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}
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}
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let region_flags = self.device.get_region_flags(region.index);
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if region_flags & VFIO_REGION_INFO_FLAG_MMAP != 0 {
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let mut prot = 0;
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if region_flags & VFIO_REGION_INFO_FLAG_READ != 0 {
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prot |= libc::PROT_READ;
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}
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if region_flags & VFIO_REGION_INFO_FLAG_WRITE != 0 {
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prot |= libc::PROT_WRITE;
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}
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let (mmap_offset, mmap_size) = self.device.get_region_mmap(region.index);
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let offset = self.device.get_region_offset(region.index) + mmap_offset;
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let host_addr = unsafe {
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libc::mmap(
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null_mut(),
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mmap_size as usize,
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prot,
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libc::MAP_SHARED,
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fd,
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offset as libc::off_t,
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)
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};
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if host_addr == libc::MAP_FAILED {
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error!(
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"Could not mmap regions, error:{}",
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io::Error::last_os_error()
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);
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continue;
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}
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let slot = mem_slot();
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let mem_region = vm.make_user_memory_region(
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slot,
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region.start.raw_value() + mmap_offset,
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mmap_size as u64,
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host_addr as u64,
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false,
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false,
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);
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vm.create_user_memory_region(mem_region)
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.map_err(VfioPciError::MapRegionGuest)?;
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// Update the region with memory mapped info.
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region.mem_slot = Some(slot);
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region.host_addr = Some(host_addr as u64);
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region.mmap_size = Some(mmap_size as usize);
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}
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}
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Ok(())
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}
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pub fn unmap_mmio_regions(&mut self) {
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for region in self.common.mmio_regions.iter() {
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if let (Some(host_addr), Some(mmap_size), Some(mem_slot)) =
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(region.host_addr, region.mmap_size, region.mem_slot)
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{
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let (mmap_offset, _) = self.device.get_region_mmap(region.index);
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// Remove region
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let r = self.vm.make_user_memory_region(
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mem_slot,
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region.start.raw_value() + mmap_offset,
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mmap_size as u64,
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host_addr as u64,
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false,
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false,
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);
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if let Err(e) = self.vm.remove_user_memory_region(r) {
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error!("Could not remove the userspace memory region: {}", e);
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}
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let ret = unsafe { libc::munmap(host_addr as *mut libc::c_void, mmap_size) };
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if ret != 0 {
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error!(
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"Could not unmap region {}, error:{}",
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region.index,
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io::Error::last_os_error()
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);
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}
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}
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}
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}
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pub fn dma_map(&self, iova: u64, size: u64, user_addr: u64) -> Result<(), VfioPciError> {
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if !self.iommu_attached {
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self.container
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.vfio_dma_map(iova, size, user_addr)
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.map_err(VfioPciError::DmaMap)?;
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}
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Ok(())
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}
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pub fn dma_unmap(&self, iova: u64, size: u64) -> Result<(), VfioPciError> {
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if !self.iommu_attached {
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self.container
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.vfio_dma_unmap(iova, size)
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.map_err(VfioPciError::DmaUnmap)?;
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}
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Ok(())
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}
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pub fn mmio_regions(&self) -> Vec<MmioRegion> {
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self.common.mmio_regions.clone()
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}
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}
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impl Drop for VfioPciDevice {
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fn drop(&mut self) {
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self.unmap_mmio_regions();
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if let Some(msix) = &self.common.interrupt.msix {
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if msix.bar.enabled() {
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self.common.disable_msix(&self.vfio_wrapper);
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}
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}
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if let Some(msi) = &self.common.interrupt.msi {
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if msi.cfg.enabled() {
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self.common.disable_msi(&self.vfio_wrapper)
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}
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}
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if self.common.interrupt.intx_in_use() {
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self.common.disable_intx(&self.vfio_wrapper);
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}
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}
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}
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impl BusDevice for VfioPciDevice {
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fn read(&mut self, base: u64, offset: u64, data: &mut [u8]) {
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self.read_bar(base, offset, data)
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}
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fn write(&mut self, base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
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self.write_bar(base, offset, data)
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}
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}
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// First BAR offset in the PCI config space.
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const PCI_CONFIG_BAR_OFFSET: u32 = 0x10;
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// Capability register offset in the PCI config space.
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const PCI_CONFIG_CAPABILITY_OFFSET: u32 = 0x34;
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// IO BAR when first BAR bit is 1.
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const PCI_CONFIG_IO_BAR: u32 = 0x1;
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// 64-bit memory bar flag.
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const PCI_CONFIG_MEMORY_BAR_64BIT: u32 = 0x4;
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// PCI config register size (4 bytes).
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const PCI_CONFIG_REGISTER_SIZE: usize = 4;
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// Number of BARs for a PCI device
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const BAR_NUMS: usize = 6;
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// PCI Header Type register index
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const PCI_HEADER_TYPE_REG_INDEX: usize = 3;
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// First BAR register index
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const PCI_CONFIG_BAR0_INDEX: usize = 4;
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// PCI ROM expansion BAR register index
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const PCI_ROM_EXP_BAR_INDEX: usize = 12;
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impl PciDevice for VfioPciDevice {
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fn allocate_bars(
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&mut self,
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allocator: &mut SystemAllocator,
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) -> Result<Vec<(GuestAddress, GuestUsize, PciBarRegionType)>, PciDeviceError> {
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self.common.allocate_bars(allocator, &self.vfio_wrapper)
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}
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fn free_bars(&mut self, allocator: &mut SystemAllocator) -> Result<(), PciDeviceError> {
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self.common.free_bars(allocator)
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}
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fn write_config_register(
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&mut self,
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reg_idx: usize,
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offset: u64,
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data: &[u8],
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) -> Option<Arc<Barrier>> {
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self.common
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.write_config_register(reg_idx, offset, data, &self.vfio_wrapper)
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}
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fn read_config_register(&mut self, reg_idx: usize) -> u32 {
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self.common
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.read_config_register(reg_idx, &self.vfio_wrapper)
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}
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fn detect_bar_reprogramming(
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&mut self,
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reg_idx: usize,
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data: &[u8],
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) -> Option<BarReprogrammingParams> {
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self.common
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.configuration
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.detect_bar_reprogramming(reg_idx, data)
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}
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fn read_bar(&mut self, base: u64, offset: u64, data: &mut [u8]) {
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self.common.read_bar(base, offset, data, &self.vfio_wrapper)
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}
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fn write_bar(&mut self, base: u64, offset: u64, data: &[u8]) -> Option<Arc<Barrier>> {
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self.common
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.write_bar(base, offset, data, &self.vfio_wrapper)
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}
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fn move_bar(&mut self, old_base: u64, new_base: u64) -> Result<(), io::Error> {
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for region in self.common.mmio_regions.iter_mut() {
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if region.start.raw_value() == old_base {
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region.start = GuestAddress(new_base);
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if let Some(mem_slot) = region.mem_slot {
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if let Some(host_addr) = region.host_addr {
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let (mmap_offset, mmap_size) = self.device.get_region_mmap(region.index);
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// Remove old region
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let old_mem_region = self.vm.make_user_memory_region(
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mem_slot,
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old_base + mmap_offset,
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mmap_size as u64,
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host_addr as u64,
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false,
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false,
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);
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self.vm
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.remove_user_memory_region(old_mem_region)
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.map_err(|e| io::Error::new(io::ErrorKind::Other, e))?;
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// Insert new region
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let new_mem_region = self.vm.make_user_memory_region(
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mem_slot,
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new_base + mmap_offset,
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mmap_size as u64,
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host_addr as u64,
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false,
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false,
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);
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self.vm
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.create_user_memory_region(new_mem_region)
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.map_err(|e| io::Error::new(io::ErrorKind::Other, e))?;
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}
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}
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}
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}
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Ok(())
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}
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fn as_any(&mut self) -> &mut dyn Any {
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self
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}
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}
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