Sebastien Boeuf bf37ebdcb6 arch: x86_64: Add 5th level of paging when needed ...

For correctness, when the CPUID supports the LA57 feature, the VMM sets
the CR4.LA57 register, which means a fifth level of page table might be
needed. Even if it's not needed because the kernel should not use
addresses over 1GiB, it's better to define this new level anyway.

This patch only applies to the Linux boot codepath, which means it
affects both vmlinux without PVH and bzImage binaries. The bzImage
does not need this since the page tables and CR4 registers are set in
the decompression code from the kernel.

And for vmlinux with PVH, if we follow the PVH specification, the kernel
must be responsible for setting things up, but the implementation is
missing. This means for now that PVH does not support LA57 with 5 levels
of paging.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>

2020-06-11 09:18:52 +02:00

..

src

arch: x86_64: Add 5th level of paging when needed

2020-06-11 09:18:52 +02:00

Cargo.toml

build(deps): bump vm-memory from 0.2.0 to 0.2.1

2020-05-28 17:06:48 +01:00