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This commit ensures device's PCI config space is being written after MSI/MSI-X interrupts have been enabled/disabled. In case of MSI, when the interrupts are enabled through VFIO (using VFIO_DEVICE_SET_IRQS), the MSI Enable bit in the MSI capability structure found in the PCI config space is disabled by default. That's why when the guest is enabling this bit, we first need to enable the MSI interrupts with VFIO through VFIO_DEVICE_SET_IRQS ioctl, and only after we can write to the device region to update the MSI Enable bit. Fixes #460 Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com> |
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Cargo.toml |