Sebastien Boeuf 23fb4fa26d pci: Allow only writable bits for MSI message control register ... The same way we mask the writes coming from the guest to the message control register related to MSI-X capability, let's do the same for MSI. The point is to prevent the guest from writing to read-only bits. The correct writable bits for MSI are only bits 0, 4, 5 and 6 of 2nd 16-bit word. Those are: * MSI Enable: 0 * Multiple Message Enable: 6-4 See "Table 7-39 Message Control Register for MSI" from "NCB-PCI_Express_Base_5.0r1.0-2019-05-22.pdf". Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>		2022-02-23 14:01:55 +01:00
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src	pci: Allow only writable bits for MSI message control register	2022-02-23 14:01:55 +01:00
Cargo.toml	build: bump libc from 0.2.118 to 0.2.119	2022-02-22 09:55:13 +00:00