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ee39e46568
In order to support use cases that require MSI, the pci crate is being expanded with the description of an MSI PCI capability structure through the new MsiCap Rust structure. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
45 lines
1.2 KiB
Rust
45 lines
1.2 KiB
Rust
// Copyright 2018 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE-BSD-3-Clause file.
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//! Implements pci devices and busses.
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#[macro_use]
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extern crate log;
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extern crate devices;
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extern crate kvm_ioctls;
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extern crate vm_memory;
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extern crate vmm_sys_util;
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mod bus;
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mod configuration;
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mod device;
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mod msi;
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mod msix;
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pub use self::bus::{PciConfigIo, PciConfigMmio, PciRoot, PciRootError};
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pub use self::configuration::{
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PciBarConfiguration, PciBarPrefetchable, PciBarRegionType, PciCapability, PciCapabilityID,
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PciClassCode, PciConfiguration, PciHeaderType, PciMassStorageSubclass,
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PciNetworkControllerSubclass, PciProgrammingInterface, PciSerialBusSubClass, PciSubclass,
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};
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pub use self::device::{
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Error as PciDeviceError, InterruptDelivery, InterruptParameters, PciDevice,
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};
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pub use self::msi::MsiCap;
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pub use self::msix::{MsixCap, MsixConfig, MsixTableEntry, MSIX_TABLE_ENTRY_SIZE};
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/// PCI has four interrupt pins A->D.
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#[derive(Copy, Clone)]
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pub enum PciInterruptPin {
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IntA,
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IntB,
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IntC,
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IntD,
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}
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impl PciInterruptPin {
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pub fn to_mask(self) -> u32 {
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self as u32
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}
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}
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