Sebastien Boeuf 1379abb94b pci: msi: Fix MSG_CTL update through 32 bits write ...

If the MSG_CTL is being written from a 32 bits write access, the offset
won't be 0x2, but 0x0 instead. That's simply because 32 bits access have
to be aligned on each double word.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>

2019-12-04 08:48:17 +01:00

..

src

pci: msi: Fix MSG_CTL update through 32 bits write

2019-12-04 08:48:17 +01:00

Cargo.toml

cargo: Bump the kvm and vmm-sys-util crates

2019-11-29 17:48:02 +00:00