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https://github.com/cloud-hypervisor/cloud-hypervisor.git
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d810c7712d
The current MSI-X implementation completely ignores the values found in the Vector Control register related to a specific vector, and never updates the Pending Bit Array. According to the PCI specification, MSI-X vectors can be masked through the Vector Control register on bit 0. If this bit is set, the device should not inject any MSI message. When the device runs into such situation, it must not inject the interrupt, but instead it must update the bit corresponding to the vector number in the Pending Bit Array. Later on, if/when the Vector Control register is updated, and if the bit 0 is flipped from 0 to 1, the device must look into the PBA to find out if there was a pending interrupt for this specific vector. If that's the case, an MSI message is injected and the bit from the PBA is cleared. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
98 lines
3.4 KiB
Rust
Executable File
98 lines
3.4 KiB
Rust
Executable File
// Copyright 2018 The Chromium OS Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE-BSD-3-Clause file.
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use crate::configuration::{self, PciConfiguration};
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use crate::msix::MsixTableEntry;
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use crate::PciInterruptPin;
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use devices::BusDevice;
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use std;
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use std::fmt::{self, Display};
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use std::sync::Arc;
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use vm_allocator::SystemAllocator;
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use vm_memory::{GuestAddress, GuestUsize};
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use vmm_sys_util::EventFd;
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pub struct InterruptParameters<'a> {
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pub msix: Option<&'a MsixTableEntry>,
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}
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pub type InterruptDelivery =
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Box<Fn(InterruptParameters) -> std::result::Result<(), std::io::Error> + Send + Sync>;
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#[derive(Debug)]
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pub enum Error {
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/// Setup of the device capabilities failed.
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CapabilitiesSetup(configuration::Error),
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/// Allocating space for an IO BAR failed.
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IoAllocationFailed(u64),
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/// Registering an IO BAR failed.
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IoRegistrationFailed(u64, configuration::Error),
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}
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pub type Result<T> = std::result::Result<T, Error>;
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impl Display for Error {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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use self::Error::*;
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match self {
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CapabilitiesSetup(e) => write!(f, "failed to add capability {}", e),
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IoAllocationFailed(size) => {
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write!(f, "failed to allocate space for an IO BAR, size={}", size)
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}
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IoRegistrationFailed(addr, e) => {
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write!(f, "failed to register an IO BAR, addr={} err={}", addr, e)
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}
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}
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}
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}
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pub trait PciDevice: BusDevice {
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/// Assign a legacy PCI IRQ to this device.
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/// The device may write to `irq_evt` to trigger an interrupt.
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fn assign_pin_irq(
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&mut self,
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_irq_cb: Arc<InterruptDelivery>,
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_irq_num: u32,
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_irq_pin: PciInterruptPin,
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) {
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}
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/// Assign MSI-X to this device.
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fn assign_msix(&mut self, _msi_cb: Arc<InterruptDelivery>) {}
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/// Allocates the needed PCI BARs space using the `allocate` function which takes a size and
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/// returns an address. Returns a Vec of (GuestAddress, GuestUsize) tuples.
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fn allocate_bars(
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&mut self,
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_allocator: &mut SystemAllocator,
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) -> Result<Vec<(GuestAddress, GuestUsize)>> {
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Ok(Vec::new())
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}
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/// Register any capabilties specified by the device.
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fn register_device_capabilities(&mut self) -> Result<()> {
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Ok(())
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}
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/// Gets a list of ioeventfds that should be registered with the running VM. The list is
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/// returned as a Vec of (eventfd, addr, datamatch) tuples.
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fn ioeventfds(&self) -> Vec<(&EventFd, u64, u64)> {
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Vec::new()
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}
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/// Gets the configuration registers of the Pci Device.
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fn config_registers(&self) -> &PciConfiguration; // TODO - remove these
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/// Gets the configuration registers of the Pci Device for modification.
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fn config_registers_mut(&mut self) -> &mut PciConfiguration;
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/// Reads from a BAR region mapped in to the device.
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/// * `addr` - The guest address inside the BAR.
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/// * `data` - Filled with the data from `addr`.
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fn read_bar(&mut self, addr: u64, data: &mut [u8]);
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/// Writes to a BAR region mapped in to the device.
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/// * `addr` - The guest address inside the BAR.
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/// * `data` - The data to write.
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fn write_bar(&mut self, addr: u64, data: &[u8]);
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/// Invoked when the device is sandboxed.
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fn on_device_sandboxed(&mut self) {}
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}
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