Sebastien Boeuf 23fb4fa26d pci: Allow only writable bits for MSI message control register ... The same way we mask the writes coming from the guest to the message control register related to MSI-X capability, let's do the same for MSI. The point is to prevent the guest from writing to read-only bits. The correct writable bits for MSI are only bits 0, 4, 5 and 6 of 2nd 16-bit word. Those are: * MSI Enable: 0 * Multiple Message Enable: 6-4 See "Table 7-39 Message Control Register for MSI" from "NCB-PCI_Express_Base_5.0r1.0-2019-05-22.pdf". Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>		2022-02-23 14:01:55 +01:00
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bus.rs	vmm: Use PciBdf throughout in order to remove manual bit manipulation	2021-11-02 16:55:42 +00:00
configuration.rs	pci: Allow only writable bits for MSI message control register	2022-02-23 14:01:55 +01:00
device.rs	vmm, pci: Fix potential deadlock in PCI BAR allocation	2022-01-06 09:59:36 +01:00
lib.rs	pci, vmm: Update DeviceNode to store PciBdf instead of u32	2022-02-16 11:57:23 +00:00
msi.rs	clippy: Fix redundant allocations	2021-07-29 13:28:57 +02:00
msix.rs	pci: add debug output for enabling and disabling MSI-X	2022-02-17 17:33:40 +01:00
vfio_user.rs	pci, vmm: Pass PCI BDF to vfio and vfio_user	2022-01-18 18:00:00 -08:00
vfio.rs	pci, vmm: Pass PCI BDF to vfio and vfio_user	2022-01-18 18:00:00 -08:00