mirror of
https://github.com/cloud-hypervisor/cloud-hypervisor.git
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28a5f9dc19
The IORT table for virtio-iommu use was removed and replaced with a purely virtio based solution. Although the table construction was removed these structures were left behind. Signed-off-by: Rob Bradford <robert.bradford@intel.com>
142 lines
4.0 KiB
Rust
142 lines
4.0 KiB
Rust
// Copyright © 2019 Intel Corporation
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//
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// SPDX-License-Identifier: Apache-2.0
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//
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use acpi_tables::{
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aml::Aml,
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rsdp::RSDP,
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sdt::{GenericAddress, SDT},
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};
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use vm_memory::{GuestAddress, GuestMemoryMmap};
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use vm_memory::{Address, ByteValued, Bytes};
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use std::sync::{Arc, Mutex};
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use crate::cpu::CpuManager;
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use crate::device_manager::DeviceManager;
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use crate::memory_manager::MemoryManager;
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use arch::layout;
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#[repr(packed)]
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#[derive(Default)]
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struct PCIRangeEntry {
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pub base_address: u64,
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pub segment: u16,
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pub start: u8,
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pub end: u8,
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_reserved: u32,
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}
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pub fn create_dsdt_table(
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device_manager: &Arc<Mutex<DeviceManager>>,
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cpu_manager: &Arc<Mutex<CpuManager>>,
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memory_manager: &Arc<Mutex<MemoryManager>>,
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) -> SDT {
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// DSDT
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let mut dsdt = SDT::new(*b"DSDT", 36, 6, *b"CLOUDH", *b"CHDSDT ", 1);
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dsdt.append_slice(device_manager.lock().unwrap().to_aml_bytes().as_slice());
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dsdt.append_slice(cpu_manager.lock().unwrap().to_aml_bytes().as_slice());
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dsdt.append_slice(memory_manager.lock().unwrap().to_aml_bytes().as_slice());
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dsdt
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}
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pub fn create_acpi_tables(
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guest_mem: &GuestMemoryMmap,
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device_manager: &Arc<Mutex<DeviceManager>>,
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cpu_manager: &Arc<Mutex<CpuManager>>,
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memory_manager: &Arc<Mutex<MemoryManager>>,
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) -> GuestAddress {
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// RSDP is at the EBDA
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let rsdp_offset = layout::RSDP_POINTER;
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let mut tables: Vec<u64> = Vec::new();
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// DSDT
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let dsdt = create_dsdt_table(device_manager, cpu_manager, memory_manager);
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let dsdt_offset = rsdp_offset.checked_add(RSDP::len() as u64).unwrap();
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guest_mem
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.write_slice(dsdt.as_slice(), dsdt_offset)
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.expect("Error writing DSDT table");
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// FACP aka FADT
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// Revision 6 of the ACPI FADT table is 276 bytes long
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let mut facp = SDT::new(*b"FACP", 276, 6, *b"CLOUDH", *b"CHFACP ", 1);
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// HW_REDUCED_ACPI and RESET_REG_SUP
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let fadt_flags: u32 = 1 << 20 | 1 << 10;
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facp.write(112, fadt_flags);
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// RESET_REG
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facp.write(116, GenericAddress::io_port_address(0x3c0));
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// RESET_VALUE
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facp.write(128, 1u8);
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facp.write(131, 3u8); // FADT minor version
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facp.write(140, dsdt_offset.0); // X_DSDT
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// SLEEP_CONTROL_REG
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facp.write(244, GenericAddress::io_port_address(0x3c0));
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// SLEEP_STATUS_REG
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facp.write(256, GenericAddress::io_port_address(0x3c0));
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facp.write(268, b"CLOUDHYP"); // Hypervisor Vendor Identity
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facp.update_checksum();
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let facp_offset = dsdt_offset.checked_add(dsdt.len() as u64).unwrap();
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guest_mem
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.write_slice(facp.as_slice(), facp_offset)
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.expect("Error writing FACP table");
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tables.push(facp_offset.0);
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// MADT
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let madt = cpu_manager.lock().unwrap().create_madt();
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let madt_offset = facp_offset.checked_add(facp.len() as u64).unwrap();
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guest_mem
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.write_slice(madt.as_slice(), madt_offset)
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.expect("Error writing MADT table");
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tables.push(madt_offset.0);
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// MCFG
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let mut mcfg = SDT::new(*b"MCFG", 36, 1, *b"CLOUDH", *b"CHMCFG ", 1);
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// MCFG reserved 8 bytes
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mcfg.append(0u64);
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// 32-bit PCI enhanced configuration mechanism
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mcfg.append(PCIRangeEntry {
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base_address: layout::PCI_MMCONFIG_START.0,
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segment: 0,
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start: 0,
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end: 0xff,
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..Default::default()
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});
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let mcfg_offset = madt_offset.checked_add(madt.len() as u64).unwrap();
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guest_mem
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.write_slice(mcfg.as_slice(), mcfg_offset)
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.expect("Error writing MCFG table");
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tables.push(mcfg_offset.0);
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// XSDT
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let mut xsdt = SDT::new(*b"XSDT", 36, 1, *b"CLOUDH", *b"CHXSDT ", 1);
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for table in tables {
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xsdt.append(table);
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}
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xsdt.update_checksum();
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let xsdt_offset = mcfg_offset.checked_add(mcfg.len() as u64).unwrap();
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guest_mem
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.write_slice(xsdt.as_slice(), xsdt_offset)
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.expect("Error writing XSDT table");
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// RSDP
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let rsdp = RSDP::new(*b"CLOUDH", xsdt_offset.0);
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guest_mem
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.write_slice(rsdp.as_slice(), rsdp_offset)
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.expect("Error writing RSDP");
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rsdp_offset
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}
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