Rob Bradford ffaab46934 misc: Use a more relaxed memory model when possible ... When a total ordering between multiple atomic variables is not required then use Ordering::Acquire with atomic loads and Ordering::Release with atomic stores. This will improve performance as this does not require a memory fence on x86_64 which Ordering::SeqCst will use. Add a comment to the code in the vCPU handling code where it operates on multiple atomics to explain why Ordering::SeqCst is required. Signed-off-by: Rob Bradford <robert.bradford@intel.com>		2020-12-02 19:04:30 +01:00
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src	misc: Use a more relaxed memory model when possible	2020-12-02 19:04:30 +01:00
Cargo.toml	build(deps): bump signal-hook from 0.2.0 to 0.2.1	2020-11-25 00:26:27 +00:00