libvirt/tests/cputestdata/x86_64-cpuid-Core-i5-4670T-json.xml

<cpu mode='custom' match='exact'>
  <model fallback='forbid'>Haswell-noTSX</model>
  <vendor>Intel</vendor>
  <feature policy='require' name='vme'/>
  <feature policy='require' name='ss'/>
  <feature policy='require' name='vmx'/>
  <feature policy='require' name='f16c'/>
  <feature policy='require' name='rdrand'/>
  <feature policy='require' name='hypervisor'/>
  <feature policy='require' name='tsc_adjust'/>
  <feature policy='require' name='xsaveopt'/>
  <feature policy='require' name='pdpe1gb'/>
  <feature policy='require' name='abm'/>
</cpu>
tests: Add CPU detection test for Intel Core i5-4670T Signed-off-by: Jiri Denemark <jdenemar@redhat.com> 2016-06-01 15:52:51 +00:00			`<cpu mode='custom' match='exact'>`
cpu_x86: Disable TSX on broken models All Intel Haswell processors (except Xeon E7 v3 with stepping >= 4) have TSX disabled by microcode update. As not all CPUs are guaranteed to be patched with microcode updates we need to explicitly disable TSX on affected CPUs to avoid its accidental usage. https://bugzilla.redhat.com/show_bug.cgi?id=1406791 Signed-off-by: Jiri Denemark <jdenemar@redhat.com> 2017-02-15 14:01:40 +00:00			`<model fallback='forbid'>Haswell-noTSX</model>`
cputest: Test virQEMUCapsInitCPUModel The original test didn't use family/model numbers to make better decisions about the CPU model and thus mis-detected the model in the two cases which are modified in this commit. The detected CPU models now match those obtained from raw CPUID data. Signed-off-by: Jiri Denemark <jdenemar@redhat.com> 2017-02-13 09:33:52 +00:00			`<vendor>Intel</vendor>`
tests: Add CPU detection test for Intel Core i5-4670T Signed-off-by: Jiri Denemark <jdenemar@redhat.com> 2016-06-01 15:52:51 +00:00			`<feature policy='require' name='vme'/>`
			`<feature policy='require' name='ss'/>`
			`<feature policy='require' name='vmx'/>`
			`<feature policy='require' name='f16c'/>`
			`<feature policy='require' name='rdrand'/>`
			`<feature policy='require' name='hypervisor'/>`
cpu: Sort CPU map features on eax_in As a side effect this changes the order of CPU features in XMLs generated by libvirt, but that's not a big deal since the order there is insignificant. Signed-off-by: Jiri Denemark <jdenemar@redhat.com> 2016-06-01 13:40:09 +00:00			`<feature policy='require' name='tsc_adjust'/>`
cpu: Add x86 feature flags for CPUID leaf 0xd, sub leaf 1 This was implemented in QEMU by commit 0bb0b2d2fe7f645dda. Signed-off-by: Jiri Denemark <jdenemar@redhat.com> 2016-05-23 15:57:39 +00:00			`<feature policy='require' name='xsaveopt'/>`
tests: Add CPU detection test for Intel Core i5-4670T Signed-off-by: Jiri Denemark <jdenemar@redhat.com> 2016-06-01 15:52:51 +00:00			`<feature policy='require' name='pdpe1gb'/>`
			`<feature policy='require' name='abm'/>`
			`</cpu>`