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cpu: Add SandyBridge-IBRS CPU model
This is a variant of SandyBridge with indirect branch prediction protection. The only difference between SandyBridge and SandyBridge-IBRS is the added "spec-ctrl" feature. The SandyBridge-IBRS model in QEMU is a bit different since SandyBridge got several additional features since we added it in cpu_map.xml: arat, vme, xsaveopt Adding them only to the -IBRS variant would confuse our CPU detection code. Signed-off-by: Jiri Denemark <jdenemar@redhat.com> Reviewed-by: Pavel Hrdina <phrdina@redhat.com>
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@ -1030,6 +1030,50 @@
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<feature name='xsave'/>
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</model>
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<model name='SandyBridge-IBRS'>
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<signature family='6' model='42'/>
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<vendor name='Intel'/>
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<feature name='aes'/>
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<feature name='apic'/>
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<feature name='avx'/>
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<feature name='clflush'/>
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<feature name='cmov'/>
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<feature name='cx16'/>
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<feature name='cx8'/>
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<feature name='de'/>
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<feature name='fpu'/>
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<feature name='fxsr'/>
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<feature name='lahf_lm'/>
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<feature name='lm'/>
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<feature name='mca'/>
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<feature name='mce'/>
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<feature name='mmx'/>
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<feature name='msr'/>
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<feature name='mtrr'/>
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<feature name='nx'/>
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<feature name='pae'/>
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<feature name='pat'/>
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<feature name='pclmuldq'/>
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<feature name='pge'/>
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<feature name='pni'/>
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<feature name='popcnt'/>
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<feature name='pse'/>
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<feature name='pse36'/>
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<feature name='rdtscp'/>
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<feature name='sep'/>
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<feature name='spec-ctrl'/>
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<feature name='sse'/>
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<feature name='sse2'/>
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<feature name='sse4.1'/>
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<feature name='sse4.2'/>
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<feature name='ssse3'/>
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<feature name='syscall'/>
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<feature name='tsc'/>
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<feature name='tsc-deadline'/>
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<feature name='x2apic'/>
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<feature name='xsave'/>
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</model>
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<model name='IvyBridge'>
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<signature family='6' model='58'/>
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<vendor name='Intel'/>
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