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perf: add more perf events support
With current perf framework, this patch adds support and documentation for more perf events, including cache misses, cache references, cpu cycles, and instructions. Signed-off-by: Qiaowei Ren <qiaowei.ren@intel.com>
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@ -1922,6 +1922,10 @@
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<event name='cmt' enabled='yes'/>
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<event name='cmt' enabled='yes'/>
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<event name='mbmt' enabled='no'/>
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<event name='mbmt' enabled='no'/>
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<event name='mbml' enabled='yes'/>
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<event name='mbml' enabled='yes'/>
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<event name='cpu_cycles' enabled='no'/>
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<event name='instructions' enabled='yes'/>
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<event name='cache_references' enabled='no'/>
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<event name='cache_misses' enabled='no'/>
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</perf>
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</perf>
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...
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...
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</pre>
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</pre>
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@ -1947,6 +1951,26 @@
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<td>bandwidth of memory traffic for a memory controller</td>
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<td>bandwidth of memory traffic for a memory controller</td>
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<td><code>perf.mbml</code></td>
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<td><code>perf.mbml</code></td>
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</tr>
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</tr>
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<tr>
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<td><code>cpu_cycles</code></td>
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<td>the number of cpu cycles one instruction needs</td>
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<td><code>perf.cpu_cycles</code></td>
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</tr>
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<tr>
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<td><code>instructions</code></td>
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<td>the count of instructions by applications running on the platform</td>
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<td><code>perf.instructions</code></td>
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</tr>
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<tr>
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<td><code>cache_references</code></td>
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<td>the count of cache hits by applications running on the platform</td>
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<td><code>perf.cache_references</code></td>
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</tr>
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<tr>
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<td><code>cache_misses</code></td>
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<td>the count of cache misses by applications running on the platform</td>
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<td><code>perf.cache_misses</code></td>
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</tr>
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</table>
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</table>
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<h3><a name="elementsDevices">Devices</a></h3>
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<h3><a name="elementsDevices">Devices</a></h3>
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@ -422,6 +422,10 @@
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<value>cmt</value>
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<value>cmt</value>
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<value>mbmt</value>
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<value>mbmt</value>
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<value>mbml</value>
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<value>mbml</value>
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<value>cpu_cycles</value>
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<value>instructions</value>
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<value>cache_references</value>
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<value>cache_misses</value>
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</choice>
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</choice>
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</attribute>
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</attribute>
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<attribute name="enabled">
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<attribute name="enabled">
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@ -1972,6 +1972,45 @@ void virDomainStatsRecordListFree(virDomainStatsRecordPtr *stats);
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*/
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*/
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# define VIR_PERF_PARAM_MBML "mbml"
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# define VIR_PERF_PARAM_MBML "mbml"
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/**
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* VIR_PERF_PARAM_CACHE_MISSES:
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*
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* Macro for typed parameter name that represents cache_misses perf
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* event which can be used to measure the count of cache misses by
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* applications running on the platform. It corresponds to the
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* "perf.cache_misses" field in the *Stats APIs.
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*/
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# define VIR_PERF_PARAM_CACHE_MISSES "cache_misses"
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/**
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* VIR_PERF_PARAM_CACHE_REFERENCES:
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*
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* Macro for typed parameter name that represents cache_references
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* perf event which can be used to measure the count of cache hits
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* by applications running on the platform. It corresponds to the
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* "perf.cache_references" field in the *Stats APIs.
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*/
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# define VIR_PERF_PARAM_CACHE_REFERENCES "cache_references"
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/**
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* VIR_PERF_PARAM_INSTRUCTIONS:
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*
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* Macro for typed parameter name that represents instructions perf
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* event which can be used to measure the count of instructions
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* by applications running on the platform. It corresponds to the
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* "perf.instructions" field in the *Stats APIs.
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*/
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# define VIR_PERF_PARAM_INSTRUCTIONS "instructions"
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/**
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* VIR_PERF_PARAM_CPU_CYCLES:
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*
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* Macro for typed parameter name that represents cpu_cycles perf event
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* which can be used to measure how many cpu cycles one instruction needs.
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* It corresponds to the "perf.cpu_cycles" field in the *Stats APIs.
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*/
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# define VIR_PERF_PARAM_CPU_CYCLES "cpu_cycles"
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int virDomainGetPerfEvents(virDomainPtr dom,
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int virDomainGetPerfEvents(virDomainPtr dom,
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virTypedParameterPtr *params,
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virTypedParameterPtr *params,
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int *nparams,
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int *nparams,
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@ -11457,6 +11457,15 @@ virConnectGetDomainCapabilities(virConnectPtr conn,
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* "perf.mbml" - the amount of data (bytes/s) sent through the memory controller
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* "perf.mbml" - the amount of data (bytes/s) sent through the memory controller
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* on the socket as unsigned long long. It is produced by mbml
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* on the socket as unsigned long long. It is produced by mbml
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* perf event.
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* perf event.
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* "perf.cache_misses" - the count of cache misses as unsigned long long.
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* It is produced by cache_misses perf event.
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* "perf.cache_references" - the count of cache hits as unsigned long long.
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* It is produced by cache_references perf event.
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* "perf.instructions" - The count of instructions as unsigned long long.
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* It is produced by instructions perf event.
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* "perf.cpu_cycles" - The number of cpu cycles one instruction needs as
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* unsigned long long. It is produced by cpu_cycles
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* perf event.
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*
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*
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* Note that entire stats groups or individual stat fields may be missing from
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* Note that entire stats groups or individual stat fields may be missing from
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* the output in case they are not supported by the given hypervisor, are not
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* the output in case they are not supported by the given hypervisor, are not
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@ -9759,6 +9759,10 @@ qemuDomainSetPerfEvents(virDomainPtr dom,
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VIR_PERF_PARAM_CMT, VIR_TYPED_PARAM_BOOLEAN,
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VIR_PERF_PARAM_CMT, VIR_TYPED_PARAM_BOOLEAN,
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VIR_PERF_PARAM_MBMT, VIR_TYPED_PARAM_BOOLEAN,
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VIR_PERF_PARAM_MBMT, VIR_TYPED_PARAM_BOOLEAN,
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VIR_PERF_PARAM_MBML, VIR_TYPED_PARAM_BOOLEAN,
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VIR_PERF_PARAM_MBML, VIR_TYPED_PARAM_BOOLEAN,
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VIR_PERF_PARAM_CPU_CYCLES, VIR_TYPED_PARAM_BOOLEAN,
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VIR_PERF_PARAM_INSTRUCTIONS, VIR_TYPED_PARAM_BOOLEAN,
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VIR_PERF_PARAM_CACHE_REFERENCES, VIR_TYPED_PARAM_BOOLEAN,
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VIR_PERF_PARAM_CACHE_MISSES, VIR_TYPED_PARAM_BOOLEAN,
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NULL) < 0)
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NULL) < 0)
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return -1;
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return -1;
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@ -38,7 +38,9 @@ VIR_LOG_INIT("util.perf");
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#define VIR_FROM_THIS VIR_FROM_PERF
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#define VIR_FROM_THIS VIR_FROM_PERF
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VIR_ENUM_IMPL(virPerfEvent, VIR_PERF_EVENT_LAST,
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VIR_ENUM_IMPL(virPerfEvent, VIR_PERF_EVENT_LAST,
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"cmt", "mbmt", "mbml");
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"cmt", "mbmt", "mbml",
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"cpu_cycles", "instructions",
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"cache_references", "cache_misses");
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struct virPerfEvent {
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struct virPerfEvent {
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int type;
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int type;
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@ -71,6 +73,18 @@ static struct virPerfEventAttr attrs[] = {
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{.type = VIR_PERF_EVENT_CMT, .attrType = 0, .attrConfig = 1},
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{.type = VIR_PERF_EVENT_CMT, .attrType = 0, .attrConfig = 1},
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{.type = VIR_PERF_EVENT_MBMT, .attrType = 0, .attrConfig = 2},
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{.type = VIR_PERF_EVENT_MBMT, .attrType = 0, .attrConfig = 2},
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{.type = VIR_PERF_EVENT_MBML, .attrType = 0, .attrConfig = 3},
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{.type = VIR_PERF_EVENT_MBML, .attrType = 0, .attrConfig = 3},
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{.type = VIR_PERF_EVENT_CPU_CYCLES,
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.attrType = PERF_TYPE_HARDWARE,
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.attrConfig = PERF_COUNT_HW_CPU_CYCLES},
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{.type = VIR_PERF_EVENT_INSTRUCTIONS,
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.attrType = PERF_TYPE_HARDWARE,
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.attrConfig = PERF_COUNT_HW_INSTRUCTIONS},
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{.type = VIR_PERF_EVENT_CACHE_REFERENCES,
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.attrType = PERF_TYPE_HARDWARE,
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.attrConfig = PERF_COUNT_HW_CACHE_REFERENCES},
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{.type = VIR_PERF_EVENT_CACHE_MISSES,
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.attrType = PERF_TYPE_HARDWARE,
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.attrConfig = PERF_COUNT_HW_CACHE_MISSES},
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};
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};
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typedef struct virPerfEventAttr *virPerfEventAttrPtr;
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typedef struct virPerfEventAttr *virPerfEventAttrPtr;
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@ -32,6 +32,11 @@ typedef enum {
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VIR_PERF_EVENT_MBMT, /* Memory Bandwidth Monitoring Total */
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VIR_PERF_EVENT_MBMT, /* Memory Bandwidth Monitoring Total */
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VIR_PERF_EVENT_MBML, /* Memory Bandwidth Monitor Limit for controller */
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VIR_PERF_EVENT_MBML, /* Memory Bandwidth Monitor Limit for controller */
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VIR_PERF_EVENT_CPU_CYCLES, /* CPU Cycles per instruction */
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VIR_PERF_EVENT_INSTRUCTIONS, /* Count of instructions for application */
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VIR_PERF_EVENT_CACHE_REFERENCES, /* Cache hits by applications */
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VIR_PERF_EVENT_CACHE_MISSES, /* Cache misses by applications */
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VIR_PERF_EVENT_LAST
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VIR_PERF_EVENT_LAST
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} virPerfEventType;
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} virPerfEventType;
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@ -16,6 +16,10 @@
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<event name='cmt' enabled='yes'/>
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<event name='cmt' enabled='yes'/>
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<event name='mbmt' enabled='no'/>
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<event name='mbmt' enabled='no'/>
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<event name='mbml' enabled='yes'/>
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<event name='mbml' enabled='yes'/>
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<event name='cpu_cycles' enabled='no'/>
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<event name='instructions' enabled='yes'/>
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<event name='cache_references' enabled='no'/>
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<event name='cache_misses' enabled='no'/>
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</perf>
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</perf>
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<devices>
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<devices>
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</devices>
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</devices>
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@ -934,6 +934,10 @@ I<--perf> returns the statistics of all enabled perf events:
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"perf.cmt" - the cache usage in Byte currently used
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"perf.cmt" - the cache usage in Byte currently used
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"perf.mbmt" - total system bandwidth from one level of cache
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"perf.mbmt" - total system bandwidth from one level of cache
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"perf.mbml" - bandwidth of memory traffic for a memory controller
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"perf.mbml" - bandwidth of memory traffic for a memory controller
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"perf.cpu_cycles" - the number of cpu cycles one instruction needs
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"perf.instructions" - the count of instructions
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"perf.cache_references" - the count of cache hits
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"perf.cache_misses" - the count of caches misses
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See the B<perf> command for more details about each event.
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See the B<perf> command for more details about each event.
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@ -2237,6 +2241,15 @@ B<Valid perf event names>
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mbml - Provides a way to limit the amount of data
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mbml - Provides a way to limit the amount of data
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(bytes/s) send through the memory controller
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(bytes/s) send through the memory controller
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on the socket.
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on the socket.
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cache_misses - Provides the count of cache misses by
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applications running on the platform.
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cache_references - Provides the count of cache hits by
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applications running on th e platform.
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instructions - Provides the count of instructions executed
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by applications running on the platform.
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cpu_cycles - Provides the number of cpu_cycles for one
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instruction. May be used with instructions
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in order to get a cycles per instruction.
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B<Note>: The statistics can be retrieved using the B<domstats> command using
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B<Note>: The statistics can be retrieved using the B<domstats> command using
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the I<--perf> flag.
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the I<--perf> flag.
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