From cd93f7ddab57fa11b03fe954f049ebcd1acd7f7a Mon Sep 17 00:00:00 2001
From: Jiri Denemark <jdenemar@redhat.com>
Date: Wed, 9 Oct 2024 14:38:21 +0200
Subject: [PATCH] cpu_map: Use compat partial check for all x86 CPU models
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
---
 src/cpu_map/x86_486.xml                       | 1 +
 src/cpu_map/x86_Broadwell-IBRS.xml            | 1 +
 src/cpu_map/x86_Broadwell-noTSX-IBRS.xml      | 1 +
 src/cpu_map/x86_Broadwell-noTSX.xml           | 1 +
 src/cpu_map/x86_Broadwell.xml                 | 1 +
 src/cpu_map/x86_Cascadelake-Server-noTSX.xml  | 1 +
 src/cpu_map/x86_Cascadelake-Server.xml        | 1 +
 src/cpu_map/x86_Conroe.xml                    | 1 +
 src/cpu_map/x86_Cooperlake.xml                | 1 +
 src/cpu_map/x86_Dhyana.xml                    | 1 +
 src/cpu_map/x86_EPYC-Genoa.xml                | 1 +
 src/cpu_map/x86_EPYC-IBPB.xml                 | 1 +
 src/cpu_map/x86_EPYC-Milan.xml                | 1 +
 src/cpu_map/x86_EPYC-Rome.xml                 | 1 +
 src/cpu_map/x86_EPYC.xml                      | 1 +
 src/cpu_map/x86_GraniteRapids.xml             | 1 +
 src/cpu_map/x86_Haswell-IBRS.xml              | 1 +
 src/cpu_map/x86_Haswell-noTSX-IBRS.xml        | 1 +
 src/cpu_map/x86_Haswell-noTSX.xml             | 1 +
 src/cpu_map/x86_Haswell.xml                   | 1 +
 src/cpu_map/x86_Icelake-Client-noTSX.xml      | 1 +
 src/cpu_map/x86_Icelake-Client.xml            | 1 +
 src/cpu_map/x86_Icelake-Server-noTSX.xml      | 1 +
 src/cpu_map/x86_Icelake-Server.xml            | 1 +
 src/cpu_map/x86_IvyBridge-IBRS.xml            | 1 +
 src/cpu_map/x86_IvyBridge.xml                 | 1 +
 src/cpu_map/x86_Nehalem-IBRS.xml              | 1 +
 src/cpu_map/x86_Nehalem.xml                   | 1 +
 src/cpu_map/x86_Opteron_G1.xml                | 1 +
 src/cpu_map/x86_Opteron_G2.xml                | 1 +
 src/cpu_map/x86_Opteron_G3.xml                | 1 +
 src/cpu_map/x86_Opteron_G4.xml                | 1 +
 src/cpu_map/x86_Opteron_G5.xml                | 1 +
 src/cpu_map/x86_Penryn.xml                    | 1 +
 src/cpu_map/x86_SandyBridge-IBRS.xml          | 1 +
 src/cpu_map/x86_SandyBridge.xml               | 1 +
 src/cpu_map/x86_SapphireRapids.xml            | 1 +
 src/cpu_map/x86_SierraForest.xml              | 1 +
 src/cpu_map/x86_Skylake-Client-IBRS.xml       | 1 +
 src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml | 1 +
 src/cpu_map/x86_Skylake-Client.xml            | 1 +
 src/cpu_map/x86_Skylake-Server-IBRS.xml       | 1 +
 src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml | 1 +
 src/cpu_map/x86_Skylake-Server.xml            | 1 +
 src/cpu_map/x86_Snowridge.xml                 | 1 +
 src/cpu_map/x86_Westmere-IBRS.xml             | 1 +
 src/cpu_map/x86_Westmere.xml                  | 1 +
 src/cpu_map/x86_athlon.xml                    | 1 +
 src/cpu_map/x86_core2duo.xml                  | 1 +
 src/cpu_map/x86_coreduo.xml                   | 1 +
 src/cpu_map/x86_cpu64-rhel5.xml               | 1 +
 src/cpu_map/x86_cpu64-rhel6.xml               | 1 +
 src/cpu_map/x86_kvm32.xml                     | 1 +
 src/cpu_map/x86_kvm64.xml                     | 1 +
 src/cpu_map/x86_n270.xml                      | 1 +
 src/cpu_map/x86_pentium.xml                   | 1 +
 src/cpu_map/x86_pentium2.xml                  | 1 +
 src/cpu_map/x86_pentium3.xml                  | 1 +
 src/cpu_map/x86_pentiumpro.xml                | 1 +
 src/cpu_map/x86_phenom.xml                    | 1 +
 src/cpu_map/x86_qemu32.xml                    | 1 +
 src/cpu_map/x86_qemu64.xml                    | 1 +
 62 files changed, 62 insertions(+)

diff --git a/src/cpu_map/x86_486.xml b/src/cpu_map/x86_486.xml
index d05b277392..7aeac147ae 100644
--- a/src/cpu_map/x86_486.xml
+++ b/src/cpu_map/x86_486.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='486'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <feature name='fpu'/>
     <feature name='pse'/>
diff --git a/src/cpu_map/x86_Broadwell-IBRS.xml b/src/cpu_map/x86_Broadwell-IBRS.xml
index 4845931420..a52db94023 100644
--- a/src/cpu_map/x86_Broadwell-IBRS.xml
+++ b/src/cpu_map/x86_Broadwell-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Broadwell-IBRS'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='61'/> <!-- 0306d0 -->
     <signature family='6' model='71'/> <!-- 040670 -->
diff --git a/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml b/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
index b1e7aa5d5e..2f4aaeb079 100644
--- a/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Broadwell-noTSX-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Broadwell-noTSX-IBRS'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='61'/> <!-- 0306d0 -->
     <signature family='6' model='71'/> <!-- 040670 -->
diff --git a/src/cpu_map/x86_Broadwell-noTSX.xml b/src/cpu_map/x86_Broadwell-noTSX.xml
index 24aa6a37bd..82f2d6d9cc 100644
--- a/src/cpu_map/x86_Broadwell-noTSX.xml
+++ b/src/cpu_map/x86_Broadwell-noTSX.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Broadwell-noTSX'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='61'/> <!-- 0306d0 -->
     <signature family='6' model='71'/> <!-- 040670 -->
diff --git a/src/cpu_map/x86_Broadwell.xml b/src/cpu_map/x86_Broadwell.xml
index 1b27489db2..53e762f74e 100644
--- a/src/cpu_map/x86_Broadwell.xml
+++ b/src/cpu_map/x86_Broadwell.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Broadwell'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='61'/> <!-- 0306d0 -->
     <signature family='6' model='71'/> <!-- 040670 -->
diff --git a/src/cpu_map/x86_Cascadelake-Server-noTSX.xml b/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
index d1d49fdd58..3c2325562f 100644
--- a/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
+++ b/src/cpu_map/x86_Cascadelake-Server-noTSX.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Cascadelake-Server-noTSX'>
+    <check partial='compat'/>
     <decode host='on' guest='off'/>
     <signature family='6' model='85' stepping='5-7'/> <!-- 050654 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Cascadelake-Server.xml b/src/cpu_map/x86_Cascadelake-Server.xml
index 09840ce52f..1463982add 100644
--- a/src/cpu_map/x86_Cascadelake-Server.xml
+++ b/src/cpu_map/x86_Cascadelake-Server.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Cascadelake-Server'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='85' stepping='5-7'/> <!-- 050654 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Conroe.xml b/src/cpu_map/x86_Conroe.xml
index 955297ffc3..b187dd5034 100644
--- a/src/cpu_map/x86_Conroe.xml
+++ b/src/cpu_map/x86_Conroe.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Conroe'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='15'/> <!-- 0006f0 -->
     <signature family='6' model='22'/> <!-- 010660 -->
diff --git a/src/cpu_map/x86_Cooperlake.xml b/src/cpu_map/x86_Cooperlake.xml
index 8f37df60de..acb46eaf8a 100644
--- a/src/cpu_map/x86_Cooperlake.xml
+++ b/src/cpu_map/x86_Cooperlake.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Cooperlake'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='85' stepping='10-11'/> <!-- 05065b -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Dhyana.xml b/src/cpu_map/x86_Dhyana.xml
index cfde07f99f..4ee32877f7 100644
--- a/src/cpu_map/x86_Dhyana.xml
+++ b/src/cpu_map/x86_Dhyana.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Dhyana'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='24' model='0'/> <!-- 900f00 -->
     <vendor name='Hygon'/>
diff --git a/src/cpu_map/x86_EPYC-Genoa.xml b/src/cpu_map/x86_EPYC-Genoa.xml
index 3e765b89b1..d87a01fd16 100644
--- a/src/cpu_map/x86_EPYC-Genoa.xml
+++ b/src/cpu_map/x86_EPYC-Genoa.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='EPYC-Genoa'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='25' model='17'/>
     <vendor name='AMD'/>
diff --git a/src/cpu_map/x86_EPYC-IBPB.xml b/src/cpu_map/x86_EPYC-IBPB.xml
index fc5aadf52e..bb1eedf567 100644
--- a/src/cpu_map/x86_EPYC-IBPB.xml
+++ b/src/cpu_map/x86_EPYC-IBPB.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='EPYC-IBPB'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='23' model='1'/> <!-- 800f10 -->
     <vendor name='AMD'/>
diff --git a/src/cpu_map/x86_EPYC-Milan.xml b/src/cpu_map/x86_EPYC-Milan.xml
index 3055e175fa..6849ded9aa 100644
--- a/src/cpu_map/x86_EPYC-Milan.xml
+++ b/src/cpu_map/x86_EPYC-Milan.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='EPYC-Milan'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='25' model='1'/>
     <vendor name='AMD'/>
diff --git a/src/cpu_map/x86_EPYC-Rome.xml b/src/cpu_map/x86_EPYC-Rome.xml
index e54d0a48d8..355f8368ce 100644
--- a/src/cpu_map/x86_EPYC-Rome.xml
+++ b/src/cpu_map/x86_EPYC-Rome.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='EPYC-Rome'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='23' model='49'/>
     <vendor name='AMD'/>
diff --git a/src/cpu_map/x86_EPYC.xml b/src/cpu_map/x86_EPYC.xml
index 3b406de37a..9b47fbba5b 100644
--- a/src/cpu_map/x86_EPYC.xml
+++ b/src/cpu_map/x86_EPYC.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='EPYC'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='23' model='1'/> <!-- 800f10 -->
     <vendor name='AMD'/>
diff --git a/src/cpu_map/x86_GraniteRapids.xml b/src/cpu_map/x86_GraniteRapids.xml
index 9a94476459..68491a7bc1 100644
--- a/src/cpu_map/x86_GraniteRapids.xml
+++ b/src/cpu_map/x86_GraniteRapids.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='GraniteRapids'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='173'/>
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Haswell-IBRS.xml b/src/cpu_map/x86_Haswell-IBRS.xml
index 0fed6fbb78..e5b88758ad 100644
--- a/src/cpu_map/x86_Haswell-IBRS.xml
+++ b/src/cpu_map/x86_Haswell-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Haswell-IBRS'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='60'/> <!-- 0306c0 -->
     <signature family='6' model='63'/> <!-- 0306f0 -->
diff --git a/src/cpu_map/x86_Haswell-noTSX-IBRS.xml b/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
index f7bc81ba4d..0a2e7dc17c 100644
--- a/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Haswell-noTSX-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Haswell-noTSX-IBRS'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='60'/> <!-- 0306c0 -->
     <signature family='6' model='63'/> <!-- 0306f0 -->
diff --git a/src/cpu_map/x86_Haswell-noTSX.xml b/src/cpu_map/x86_Haswell-noTSX.xml
index 7d17911917..9e16212c04 100644
--- a/src/cpu_map/x86_Haswell-noTSX.xml
+++ b/src/cpu_map/x86_Haswell-noTSX.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Haswell-noTSX'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='60'/> <!-- 0306c0 -->
     <signature family='6' model='63'/> <!-- 0306f0 -->
diff --git a/src/cpu_map/x86_Haswell.xml b/src/cpu_map/x86_Haswell.xml
index b121e15d4d..3e52976240 100644
--- a/src/cpu_map/x86_Haswell.xml
+++ b/src/cpu_map/x86_Haswell.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Haswell'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='60'/> <!-- 0306c0 -->
     <signature family='6' model='63'/> <!-- 0306f0 -->
diff --git a/src/cpu_map/x86_Icelake-Client-noTSX.xml b/src/cpu_map/x86_Icelake-Client-noTSX.xml
index 217adba4f2..3c61372ca3 100644
--- a/src/cpu_map/x86_Icelake-Client-noTSX.xml
+++ b/src/cpu_map/x86_Icelake-Client-noTSX.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Icelake-Client-noTSX'>
+    <check partial='compat'/>
     <decode host='on' guest='off'/>
     <signature family='6' model='126'/> <!-- 0706e0 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Icelake-Client.xml b/src/cpu_map/x86_Icelake-Client.xml
index b725227f46..dd777f36b7 100644
--- a/src/cpu_map/x86_Icelake-Client.xml
+++ b/src/cpu_map/x86_Icelake-Client.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Icelake-Client'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='126'/> <!-- 0706e0 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Icelake-Server-noTSX.xml b/src/cpu_map/x86_Icelake-Server-noTSX.xml
index 36596433cb..d8dd8f4933 100644
--- a/src/cpu_map/x86_Icelake-Server-noTSX.xml
+++ b/src/cpu_map/x86_Icelake-Server-noTSX.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Icelake-Server-noTSX'>
+    <check partial='compat'/>
     <decode host='on' guest='off'/>
     <signature family='6' model='106'/> <!-- 0606A5 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Icelake-Server.xml b/src/cpu_map/x86_Icelake-Server.xml
index 1e7ff355d5..69dd32fb2d 100644
--- a/src/cpu_map/x86_Icelake-Server.xml
+++ b/src/cpu_map/x86_Icelake-Server.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Icelake-Server'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='106'/> <!-- 0606A5 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_IvyBridge-IBRS.xml b/src/cpu_map/x86_IvyBridge-IBRS.xml
index 324152f856..e2e01694cd 100644
--- a/src/cpu_map/x86_IvyBridge-IBRS.xml
+++ b/src/cpu_map/x86_IvyBridge-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='IvyBridge-IBRS'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='58'/> <!-- 0306a0 -->
     <signature family='6' model='62'/> <!-- 0306e0 -->
diff --git a/src/cpu_map/x86_IvyBridge.xml b/src/cpu_map/x86_IvyBridge.xml
index 49d587afab..546c2eedb8 100644
--- a/src/cpu_map/x86_IvyBridge.xml
+++ b/src/cpu_map/x86_IvyBridge.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='IvyBridge'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='58'/> <!-- 0306a0 -->
     <signature family='6' model='62'/> <!-- 0306e0 -->
diff --git a/src/cpu_map/x86_Nehalem-IBRS.xml b/src/cpu_map/x86_Nehalem-IBRS.xml
index ac05a349db..22c2e0f59e 100644
--- a/src/cpu_map/x86_Nehalem-IBRS.xml
+++ b/src/cpu_map/x86_Nehalem-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Nehalem-IBRS'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='26'/> <!-- 0106a0 -->
     <signature family='6' model='30'/> <!-- 0106e0 -->
diff --git a/src/cpu_map/x86_Nehalem.xml b/src/cpu_map/x86_Nehalem.xml
index 74b85701e8..40903a92b3 100644
--- a/src/cpu_map/x86_Nehalem.xml
+++ b/src/cpu_map/x86_Nehalem.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Nehalem'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='26'/> <!-- 0106a0 -->
     <signature family='6' model='30'/> <!-- 0106e0 -->
diff --git a/src/cpu_map/x86_Opteron_G1.xml b/src/cpu_map/x86_Opteron_G1.xml
index 57648ca93f..32c7fc9ca2 100644
--- a/src/cpu_map/x86_Opteron_G1.xml
+++ b/src/cpu_map/x86_Opteron_G1.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Opteron_G1'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='15' model='6'/> <!-- 100e60 -->
     <vendor name='AMD'/>
diff --git a/src/cpu_map/x86_Opteron_G2.xml b/src/cpu_map/x86_Opteron_G2.xml
index db961b0067..01a4d69613 100644
--- a/src/cpu_map/x86_Opteron_G2.xml
+++ b/src/cpu_map/x86_Opteron_G2.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Opteron_G2'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='15' model='6'/> <!-- 100e60 -->
     <vendor name='AMD'/>
diff --git a/src/cpu_map/x86_Opteron_G3.xml b/src/cpu_map/x86_Opteron_G3.xml
index cf00af8698..d2871b4b56 100644
--- a/src/cpu_map/x86_Opteron_G3.xml
+++ b/src/cpu_map/x86_Opteron_G3.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Opteron_G3'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='15' model='6'/> <!-- 100e60 -->
     <vendor name='AMD'/>
diff --git a/src/cpu_map/x86_Opteron_G4.xml b/src/cpu_map/x86_Opteron_G4.xml
index a7fc8d5828..527124a372 100644
--- a/src/cpu_map/x86_Opteron_G4.xml
+++ b/src/cpu_map/x86_Opteron_G4.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Opteron_G4'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='21' model='1'/> <!-- 600f10 -->
     <vendor name='AMD'/>
diff --git a/src/cpu_map/x86_Opteron_G5.xml b/src/cpu_map/x86_Opteron_G5.xml
index ff775bdcef..8f51c713aa 100644
--- a/src/cpu_map/x86_Opteron_G5.xml
+++ b/src/cpu_map/x86_Opteron_G5.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Opteron_G5'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='21' model='2'/> <!-- 600f20 -->
     <vendor name='AMD'/>
diff --git a/src/cpu_map/x86_Penryn.xml b/src/cpu_map/x86_Penryn.xml
index b31f96fa43..0c6adb9037 100644
--- a/src/cpu_map/x86_Penryn.xml
+++ b/src/cpu_map/x86_Penryn.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Penryn'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='23'/> <!-- 010670 -->
     <signature family='6' model='29'/> <!-- 0106d0 -->
diff --git a/src/cpu_map/x86_SandyBridge-IBRS.xml b/src/cpu_map/x86_SandyBridge-IBRS.xml
index d2071f3367..1601763584 100644
--- a/src/cpu_map/x86_SandyBridge-IBRS.xml
+++ b/src/cpu_map/x86_SandyBridge-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='SandyBridge-IBRS'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='42'/> <!-- 0206a0 -->
     <signature family='6' model='45'/> <!-- 0206d0 -->
diff --git a/src/cpu_map/x86_SandyBridge.xml b/src/cpu_map/x86_SandyBridge.xml
index c5d342e0d0..7ae867180e 100644
--- a/src/cpu_map/x86_SandyBridge.xml
+++ b/src/cpu_map/x86_SandyBridge.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='SandyBridge'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='42'/> <!-- 0206a0 -->
     <signature family='6' model='45'/> <!-- 0206d0 -->
diff --git a/src/cpu_map/x86_SapphireRapids.xml b/src/cpu_map/x86_SapphireRapids.xml
index 1e53b30dd3..6377175fe0 100644
--- a/src/cpu_map/x86_SapphireRapids.xml
+++ b/src/cpu_map/x86_SapphireRapids.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='SapphireRapids'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='143'/>
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_SierraForest.xml b/src/cpu_map/x86_SierraForest.xml
index caa6956e94..ea4989f329 100644
--- a/src/cpu_map/x86_SierraForest.xml
+++ b/src/cpu_map/x86_SierraForest.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='SierraForest'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='175'/>
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Skylake-Client-IBRS.xml b/src/cpu_map/x86_Skylake-Client-IBRS.xml
index 892aef2031..0b1df8fc5a 100644
--- a/src/cpu_map/x86_Skylake-Client-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Client-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Skylake-Client-IBRS'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='94'/> <!-- 0506e0 -->
     <signature family='6' model='78'/> <!-- 0406e0 -->
diff --git a/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml b/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
index 63e5a02296..8884bb4bae 100644
--- a/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Client-noTSX-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Skylake-Client-noTSX-IBRS'>
+    <check partial='compat'/>
     <decode host='on' guest='off'/>
     <signature family='6' model='94'/> <!-- 0506e0 -->
     <signature family='6' model='78'/> <!-- 0406e0 -->
diff --git a/src/cpu_map/x86_Skylake-Client.xml b/src/cpu_map/x86_Skylake-Client.xml
index 83cc6780c7..8d8ab41ddd 100644
--- a/src/cpu_map/x86_Skylake-Client.xml
+++ b/src/cpu_map/x86_Skylake-Client.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Skylake-Client'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='94'/> <!-- 0506e0 -->
     <signature family='6' model='78'/> <!-- 0406e0 -->
diff --git a/src/cpu_map/x86_Skylake-Server-IBRS.xml b/src/cpu_map/x86_Skylake-Server-IBRS.xml
index 84f67c6278..8a4552f60b 100644
--- a/src/cpu_map/x86_Skylake-Server-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Server-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Skylake-Server-IBRS'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='85' stepping='0-4'/> <!-- 050654 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml b/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
index 081e30f5ad..e469da286e 100644
--- a/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
+++ b/src/cpu_map/x86_Skylake-Server-noTSX-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Skylake-Server-noTSX-IBRS'>
+    <check partial='compat'/>
     <decode host='on' guest='off'/>
     <signature family='6' model='85' stepping='0-4'/> <!-- 050654 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Skylake-Server.xml b/src/cpu_map/x86_Skylake-Server.xml
index e814b8dcf3..e7ad70e812 100644
--- a/src/cpu_map/x86_Skylake-Server.xml
+++ b/src/cpu_map/x86_Skylake-Server.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Skylake-Server'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='85' stepping='0-4'/> <!-- 050654 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Snowridge.xml b/src/cpu_map/x86_Snowridge.xml
index b254c7d71e..8b3690adb3 100644
--- a/src/cpu_map/x86_Snowridge.xml
+++ b/src/cpu_map/x86_Snowridge.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Snowridge'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='134'/> <!-- 080665 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Westmere-IBRS.xml b/src/cpu_map/x86_Westmere-IBRS.xml
index 5d2fd81b8d..2130bec8ce 100644
--- a/src/cpu_map/x86_Westmere-IBRS.xml
+++ b/src/cpu_map/x86_Westmere-IBRS.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Westmere-IBRS'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='44'/> <!-- 0206c0 -->
     <vendor name='Intel'/>
diff --git a/src/cpu_map/x86_Westmere.xml b/src/cpu_map/x86_Westmere.xml
index abbfb186b4..102af0b46b 100644
--- a/src/cpu_map/x86_Westmere.xml
+++ b/src/cpu_map/x86_Westmere.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='Westmere'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <signature family='6' model='44'/> <!-- 0206c0 -->
     <signature family='6' model='47'/> <!-- 0206f0 -->
diff --git a/src/cpu_map/x86_athlon.xml b/src/cpu_map/x86_athlon.xml
index 81c43c81e8..38259e0c46 100644
--- a/src/cpu_map/x86_athlon.xml
+++ b/src/cpu_map/x86_athlon.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='athlon'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <vendor name='AMD'/>
     <feature name='3dnow'/>
diff --git a/src/cpu_map/x86_core2duo.xml b/src/cpu_map/x86_core2duo.xml
index ea23a6c662..623ad40559 100644
--- a/src/cpu_map/x86_core2duo.xml
+++ b/src/cpu_map/x86_core2duo.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='core2duo'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <vendor name='Intel'/>
     <feature name='apic'/>
diff --git a/src/cpu_map/x86_coreduo.xml b/src/cpu_map/x86_coreduo.xml
index 24900e637f..e934213705 100644
--- a/src/cpu_map/x86_coreduo.xml
+++ b/src/cpu_map/x86_coreduo.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='coreduo'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <vendor name='Intel'/>
     <feature name='apic'/>
diff --git a/src/cpu_map/x86_cpu64-rhel5.xml b/src/cpu_map/x86_cpu64-rhel5.xml
index 7402b7603c..f331047474 100644
--- a/src/cpu_map/x86_cpu64-rhel5.xml
+++ b/src/cpu_map/x86_cpu64-rhel5.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='cpu64-rhel5'>
+    <check partial='compat'/>
     <decode host='off' guest='off'/>
     <feature name='apic'/>
     <feature name='clflush'/>
diff --git a/src/cpu_map/x86_cpu64-rhel6.xml b/src/cpu_map/x86_cpu64-rhel6.xml
index 061939c733..b05620563e 100644
--- a/src/cpu_map/x86_cpu64-rhel6.xml
+++ b/src/cpu_map/x86_cpu64-rhel6.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='cpu64-rhel6'>
+    <check partial='compat'/>
     <decode host='off' guest='off'/>
     <feature name='apic'/>
     <feature name='clflush'/>
diff --git a/src/cpu_map/x86_kvm32.xml b/src/cpu_map/x86_kvm32.xml
index ac28c53bd0..1f2de9d477 100644
--- a/src/cpu_map/x86_kvm32.xml
+++ b/src/cpu_map/x86_kvm32.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='kvm32'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <feature name='apic'/>
     <feature name='clflush'/>
diff --git a/src/cpu_map/x86_kvm64.xml b/src/cpu_map/x86_kvm64.xml
index 970a8e73d5..f6fcf1f94c 100644
--- a/src/cpu_map/x86_kvm64.xml
+++ b/src/cpu_map/x86_kvm64.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='kvm64'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <feature name='apic'/>
     <feature name='clflush'/>
diff --git a/src/cpu_map/x86_n270.xml b/src/cpu_map/x86_n270.xml
index 5507d2ea3b..fd088902fb 100644
--- a/src/cpu_map/x86_n270.xml
+++ b/src/cpu_map/x86_n270.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='n270'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <vendor name='Intel'/>
     <feature name='apic'/>
diff --git a/src/cpu_map/x86_pentium.xml b/src/cpu_map/x86_pentium.xml
index f0a8982115..a3d1063510 100644
--- a/src/cpu_map/x86_pentium.xml
+++ b/src/cpu_map/x86_pentium.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='pentium'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <feature name='cx8'/>
     <feature name='de'/>
diff --git a/src/cpu_map/x86_pentium2.xml b/src/cpu_map/x86_pentium2.xml
index aeba082297..0d0cc97e1a 100644
--- a/src/cpu_map/x86_pentium2.xml
+++ b/src/cpu_map/x86_pentium2.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='pentium2'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <feature name='cmov'/>
     <feature name='cx8'/>
diff --git a/src/cpu_map/x86_pentium3.xml b/src/cpu_map/x86_pentium3.xml
index ab85d2967f..fd249e29f9 100644
--- a/src/cpu_map/x86_pentium3.xml
+++ b/src/cpu_map/x86_pentium3.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='pentium3'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <feature name='cmov'/>
     <feature name='cx8'/>
diff --git a/src/cpu_map/x86_pentiumpro.xml b/src/cpu_map/x86_pentiumpro.xml
index b6e061187c..f3d18db033 100644
--- a/src/cpu_map/x86_pentiumpro.xml
+++ b/src/cpu_map/x86_pentiumpro.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='pentiumpro'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <feature name='apic'/>
     <feature name='cmov'/>
diff --git a/src/cpu_map/x86_phenom.xml b/src/cpu_map/x86_phenom.xml
index f0f8ece57a..8141236233 100644
--- a/src/cpu_map/x86_phenom.xml
+++ b/src/cpu_map/x86_phenom.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='phenom'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <vendor name='AMD'/>
     <feature name='3dnow'/>
diff --git a/src/cpu_map/x86_qemu32.xml b/src/cpu_map/x86_qemu32.xml
index f3fb1959be..adb51a04d6 100644
--- a/src/cpu_map/x86_qemu32.xml
+++ b/src/cpu_map/x86_qemu32.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='qemu32'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <feature name='apic'/>
     <feature name='cmov'/>
diff --git a/src/cpu_map/x86_qemu64.xml b/src/cpu_map/x86_qemu64.xml
index 0fe207a2b4..cbb78211a6 100644
--- a/src/cpu_map/x86_qemu64.xml
+++ b/src/cpu_map/x86_qemu64.xml
@@ -1,5 +1,6 @@
 <cpus>
   <model name='qemu64'>
+    <check partial='compat'/>
     <decode host='on' guest='on'/>
     <!-- These are supported only by TCG.  KVM supports them only if the
          host does.  So we leave them out: