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cpu: Add support for al57 Intel features

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We can start qemu with a "cpu,+la57" to set 57-bit vitrual address
space. So VM can be aware that it need to enable 5-level paging.

Corresponding QEMU commits:
        al57 6c7c3c21f95dd9af8a0691c0dd29b07247984122
This commit is contained in:
Shaohe Feng 2017-12-17 18:02:44 -05:00 committed by Jiri Denemark
parent fcf30f2de1
commit e7cb9c4e23
2 changed files with 4 additions and 0 deletions
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3
src/cpu/cpu_map.xml
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@ -285,6 +285,9 @@
<feature name='ospke'>
<cpuid eax_in='0x07' ecx_in='0x00' ecx='0x00000010'/>
</feature>
<feature name='la57'>
<cpuid eax_in='0x07' ecx_in='0x00' ecx='0x00010000'/>
</feature>
<feature name='avx512-4vnniw'>
<cpuid eax_in='0x07' ecx_in='0x00' edx='0x00000004'/>

1
tests/domaincapsschemadata/qemu_2.9.0-tcg.x86_64.xml
View File

@ -43,6 +43,7 @@
<feature policy='require' name='clwb'/>
<feature policy='require' name='pku'/>
<feature policy='require' name='ospke'/>
<feature policy='require' name='la57'/>
<feature policy='require' name='xsaveopt'/>
<feature policy='require' name='xgetbv1'/>
<feature policy='require' name='mmxext'/>