External/libvirt
1
0
Fork 0
mirror of https://gitlab.com/libvirt/libvirt.git synced 2024-07-31 14:07:16 +00:00
Code Issues Packages Projects Releases Wiki Activity

schema: domain: Allow interleaving of PCI controller config elements

Browse Source 
The 'model' and 'target' element can be freely moved around.

Signed-off-by: Peter Krempa <pkrempa@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
This commit is contained in:
Peter Krempa 2022-10-13 16:13:47 +02:00
parent 1210074d5e
commit fde40ee4f4
1 changed files with 96 additions and 94 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

190
src/conf/schemas/domaincommon.rng
View File

@ -2691,103 +2691,105 @@
<attribute name="type">
<value>pci</value>
</attribute>
<optional>
<element name="model">
<attribute name="name">
<choice>
<!-- implementations of "pci-root" -->
<value>spapr-pci-host-bridge</value>
<!-- implementations of "pci-bridge" -->
<value>pci-bridge</value>
<!-- implementations of "dmi-to-pci-bridge" -->
<value>i82801b11-bridge</value>
<!-- implementations of "pcie-to-pci-bridge" -->
<value>pcie-pci-bridge</value>
<!-- implementations of "pcie-root-port" -->
<value>ioh3420</value>
<value>pcie-root-port</value>
<!-- implementations of "pcie-switch-upstream-port" -->
<value>x3130-upstream</value>
<!-- implementations of "pcie-switch-downstream-port" -->
<value>xio3130-downstream</value>
<!-- implementations of "pci-expander-bus" -->
<value>pxb</value>
<!-- implementations of "pcie-expander-bus" -->
<value>pxb-pcie</value>
</choice>
</attribute>
<empty/>
</element>
</optional>
<optional>
<element name="target">
<optional>
<attribute name="chassisNr">
<ref name="uint8"/>
<interleave>
<optional>
<element name="model">
<attribute name="name">
<choice>
<!-- implementations of "pci-root" -->
<value>spapr-pci-host-bridge</value>
<!-- implementations of "pci-bridge" -->
<value>pci-bridge</value>
<!-- implementations of "dmi-to-pci-bridge" -->
<value>i82801b11-bridge</value>
<!-- implementations of "pcie-to-pci-bridge" -->
<value>pcie-pci-bridge</value>
<!-- implementations of "pcie-root-port" -->
<value>ioh3420</value>
<value>pcie-root-port</value>
<!-- implementations of "pcie-switch-upstream-port" -->
<value>x3130-upstream</value>
<!-- implementations of "pcie-switch-downstream-port" -->
<value>xio3130-downstream</value>
<!-- implementations of "pci-expander-bus" -->
<value>pxb</value>
<!-- implementations of "pcie-expander-bus" -->
<value>pxb-pcie</value>
</choice>
</attribute>
</optional>
<optional>
<attribute name="chassis">
<ref name="uint8"/>
<empty/>
</element>
</optional>
<optional>
<element name="target">
<optional>
<attribute name="chassisNr">
<ref name="uint8"/>
</attribute>
</optional>
<optional>
<attribute name="chassis">
<ref name="uint8"/>
</attribute>
</optional>
<optional>
<attribute name="port">
<ref name="uint8"/>
</attribute>
</optional>
<optional>
<attribute name="busNr">
<ref name="uint8"/>
</attribute>
</optional>
<optional>
<attribute name="index">
<ref name="uint8"/>
</attribute>
</optional>
<optional>
<attribute name="hotplug">
<ref name="virOnOff"/>
</attribute>
</optional>
<optional>
<element name="node">
<ref name="unsignedInt"/>
</element>
</optional>
</element>
</optional>
<!-- *-root controllers have an optional element "pcihole64"-->
<choice>
<group>
<attribute name="model">
<choice>
<value>pci-root</value>
<value>pcie-root</value>
</choice>
</attribute>
</optional>
<optional>
<attribute name="port">
<ref name="uint8"/>
<optional>
<element name="pcihole64">
<ref name="scaledInteger"/>
</element>
</optional>
</group>
<group>
<attribute name="model">
<choice>
<value>pci-bridge</value>
<value>dmi-to-pci-bridge</value>
<value>pcie-to-pci-bridge</value>
<value>pcie-root-port</value>
<value>pcie-switch-upstream-port</value>
<value>pcie-switch-downstream-port</value>
<value>pci-expander-bus</value>
<value>pcie-expander-bus</value>
</choice>
</attribute>
</optional>
<optional>
<attribute name="busNr">
<ref name="uint8"/>
</attribute>
</optional>
<optional>
<attribute name="index">
<ref name="uint8"/>
</attribute>
</optional>
<optional>
<attribute name="hotplug">
<ref name="virOnOff"/>
</attribute>
</optional>
<optional>
<element name="node">
<ref name="unsignedInt"/>
</element>
</optional>
</element>
</optional>
<!-- *-root controllers have an optional element "pcihole64"-->
<choice>
<group>
<attribute name="model">
<choice>
<value>pci-root</value>
<value>pcie-root</value>
</choice>
</attribute>
<optional>
<element name="pcihole64">
<ref name="scaledInteger"/>
</element>
</optional>
</group>
<group>
<attribute name="model">
<choice>
<value>pci-bridge</value>
<value>dmi-to-pci-bridge</value>
<value>pcie-to-pci-bridge</value>
<value>pcie-root-port</value>
<value>pcie-switch-upstream-port</value>
<value>pcie-switch-downstream-port</value>
<value>pci-expander-bus</value>
<value>pcie-expander-bus</value>
</choice>
</attribute>
</group>
</choice>
</group>
</choice>
</interleave>
</group>
<!-- virtio-serial has optional "ports" and "vectors" -->
<group>