Commit Graph

16 Commits

Author SHA1 Message Date
Jiri Denemark
96a39aad70 cpu_map: Add missing AMD SVM features
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2020-06-19 21:59:31 +02:00
Jiri Denemark
892b7c70f6 cpu_map: Add missing x86 features in 0x80000008 CPUID leaf
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2020-06-19 21:59:31 +02:00
Jiri Denemark
6ea3bb19c6 cpu_map: Add missing x86 features in 0x7 CPUID leaf
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2020-06-19 21:59:31 +02:00
Jiri Denemark
df69263c26 cpu_map: Request test files update when adding x86 features
The CPUID data in *-{disabled,enabled}.xml convert feature names from
the corresponding *.json file into raw CPUID and MSR data and thus some
of them may need to be updated when new features are added into the CPU
map.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2020-06-19 21:59:31 +02:00
Jiri Denemark
12eb0c9496 cpu_map: Add pschange-mc-no bit in IA32_ARCH_CAPABILITIES MSR
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Pavel Hrdina <phrdina@redhat.com>
2020-05-25 19:20:21 +02:00
Jiri Denemark
b570139909 cpu_map/x86: Add support for BFLOAT16 data type
Introduced in QEMU by commit v4.1.0-266-g80db491da4.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2020-01-07 09:07:40 +01:00
Ani Sinha
1d17f881a2 cpu: add CLZERO CPUID support for AMD platforms
Qemu commit e900135dcfb67 ("i386: Add CPUID bit for CLZERO and XSAVEERPTR")
adds support for CLZERO CPUID bit.
This commit extends support for this CPUID bit into libvirt.

Signed-off-by: Ani Sinha <ani.sinha@nutanix.com>
Message-Id: <1575371352-99055-1-git-send-email-ani.sinha@nutanix.com>
Reviewed-by: Jiri Denemark <jdenemar@redhat.com>
2019-12-16 13:04:14 +01:00
Jiri Denemark
f411b7ef68 cpu_map: Add TSX_CTRL bit for IA32_ARCH_CAPABILITIES MSR
CVE-2019-11135

When TSX_CTRL bit of IA32_ARCH_CAPABILITIES MSR is set to 1, the CPU
supports IA32_TSX_CTRL MSR which can be used to disable and/or mask TSX.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-12-13 13:25:27 +01:00
Jiri Denemark
07aaced4e6 cpu_map: Add TAA_NO bit for IA32_ARCH_CAPABILITIES MSR
CVE-2019-11135

CPUs with TAA_NO bit of IA32_ARCH_CAPABILITIES MSR set to 1 are not
vulnerable to TSX Asynchronous Abort and passing this bit to a guest
may avoid unnecessary mitigations.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-12-13 13:25:27 +01:00
Jiri Denemark
c8ec678fd9 cpu_map: Introduce IA32_ARCH_CAPABILITIES MSR features
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-06-20 14:02:36 +02:00
Jiri Denemark
538d873571 cpu_map: Define md-clear CPUID bit
CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091

The bit is set when microcode provides the mechanism to invoke a flush
of various exploitable CPU buffers by invoking the VERW instruction.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2019-05-14 19:33:37 +02:00
Jiri Denemark
8feeee9ee2 cpu_map: Add support for cldemote CPU feature
Added in QEMU by v2.12.0-481-g0da0fb0628 (released in 3.0).

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-04-25 16:26:46 +02:00
Jiri Denemark
511df17aec cpu_map: Add support for arch-capabilities feature
The feature was added to QEMU in 3.1.0 and it is currently blocking
migration, which is expected to change in the future. Luckily 3.1.0 is
new enough to give us migratability hints on each feature via
query-cpu-model-expension, which means we don't need to use the
"migratable" attribute on the CPU map XML.

The kernel calls this feature arch_capabilities and RHEL/CentOS 7.* use
arch-facilities. Apparently some CPU test files were gathered with the
RHEL version of QEMU. Let's update the test files to avoid possible
confusion about the correct naming.

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2019-01-10 16:39:57 +01:00
Jiri Denemark
eb1b551d21 cpu: Add support for "stibp" x86_64 feature
QEMU commit v3.1.0-4-g0e89165829
KVM patch: https://lore.kernel.org/lkml/20181205191956.31480-1-ehabkost@redhat.com/

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
Reviewed-by: Ján Tomko <jtomko@redhat.com>
2018-12-17 17:27:32 +01:00
Jiri Denemark
9813081119 cpu_map: Add features for Icelake CPUs
QEMU commits:

    e37a5c7fa4 (v2.12.0)
        i386: Add Intel Processor Trace feature support

    c2f193b538 (v2.7.0)
        target-i386: Add support for UMIP and RDPID CPUID bits

    aff9e6e46a (v2.12.0)
        x86/cpu: Enable new SSE/AVX/AVX512 cpu features

    f77543772d (v2.9.0)
        x86: add AVX512_VPOPCNTDQ features

    5131dc433d (v3.1.0)
        i386: Add CPUID bit for PCONFIG

    59a80a19ca (v3.1.0)
        i386: Add CPUID bit for WBNOINVD

Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
2018-09-19 14:05:59 +02:00
Daniel P. Berrangé
e6d7be38b9 cpu: split x86 map data into separate files
Reviewed-by: Jiri Denemark <jdenemar@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2018-08-28 12:08:21 +01:00